公开(公告)号：US07663397B2

公开(公告)日：2010-02-16

申请号：US12005392

申请日：2007-12-27

申请人： Jeong Suk Yang ,  Jin Ho Ryu

发明人： Jeong Suk Yang ,  Jin Ho Ryu

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/0005

摘要： A semiconductor device according to example embodiments that may include an on-die termination (ODT) control circuit having a pipe line structure which changes in response to a frequency of a clock signal and a termination resistance generator for generating termination resistance in response to a termination resistance control signal.

摘要翻译： 根据示例实施例的半导体器件可以包括管芯端接（ODT）控制电路，其具有响应于时钟信号的频率而变化的管线结构和终端电阻发生器，用于响应于终端产生终端电阻 电阻控制信号。

公开(公告)号：US20080191734A1

公开(公告)日：2008-08-14

申请号：US12005392

申请日：2007-12-27

申请人： Jeong Suk Yang ,  Jin Ho Ryu

发明人： Jeong Suk Yang ,  Jin Ho Ryu

IPC分类号： H03K17/16

CPC分类号： H03K19/0005

摘要： A semiconductor device according to example embodiments that may include an on-die termination (ODT) control circuit having a pipe line structure which changes in response to a frequency of a clock signal and a termination resistance generator for generating termination resistance in response to a termination resistance control signal.

摘要翻译： 根据示例实施例的半导体器件可以包括具有响应于时钟信号的频率而变化的管线结构的管芯端接（ODT）控制电路和用于响应于终止产生终端电阻的终端电阻发生器 电阻控制信号。

公开(公告)号：US06839286B2

公开(公告)日：2005-01-04

申请号：US10353990

申请日：2003-01-30

申请人： Uk-Rae Cho ,  Tae-Hyoung Kim ,  Jeong-Suk Yang

发明人： Uk-Rae Cho ,  Tae-Hyoung Kim ,  Jeong-Suk Yang

IPC分类号： G11C7/10 ,  G11C16/06 ,  G11C11/34

CPC分类号： G11C29/028 ,  G11C16/06 ,  G11C2029/5002

摘要： An output impedance control circuit of a semiconductor device. A first transistor is connected to a pad and a level controller controls a gate voltage of the first transistor in response to a voltage of the pad and a reference voltage. A MOS array is connected between the pad and a power supply voltage and supplies current to the pad in response to an impedance control code. A first control circuit generates the impedance control code in response to whether a voltage of the pad is converging to the reference voltage. A second control circuit controls a pull-up impedance of the output buffer circuit in response to the first impedance control code when a voltage of the pad is converging to the reference voltage.

公开(公告)号：US20080101140A1

公开(公告)日：2008-05-01

申请号：US11928022

申请日：2007-10-30

申请人： Byung-hoon JEONG ,  Seung-bum KO ,  Jeong-suk YANG

发明人： Byung-hoon JEONG ,  Seung-bum KO ,  Jeong-suk YANG

IPC分类号： G11C8/18

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： Embodiments of the invention provide a column address strobe (CAS) latency circuit that generates a stable latency signal in a high-speed semiconductor memory device, and a semiconductor memory device including the CAS latency circuit. The CAS latency circuit may include an internal read command signal generator and a latency clock generator coupled to a latency signal generator. In an embodiment of the invention, the latency signal generator outputs a stable latency signal by shifting an internal read signal output from the internal read command signal generator based on latency control clocks output from the latency clock generator.

摘要翻译： 本发明的实施例提供了一种在高速半导体存储器件中产生稳定等待时间信号的列地址选通（CAS）延迟电路，以及包括CAS等待电路的半导体存储器件。 CAS等待时间电路可以包括内部读命令信号发生器和耦合到等待时间信号发生器的等待时钟发生器。 在本发明的一个实施例中，等待时间信号发生器通过基于从等待时钟发生器输出的等待时间控制时钟移位从内部读取命令信号发生器输出的内部读取信号来输出稳定的等待时间信号。

公开(公告)号：US07675797B2

公开(公告)日：2010-03-09

申请号：US11928022

申请日：2007-10-30

申请人： Byung-hoon Jeong ,  Seung-bum Ko ,  Jeong-suk Yang

发明人： Byung-hoon Jeong ,  Seung-bum Ko ,  Jeong-suk Yang

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： Embodiments of the invention provide a column address strobe (CAS) latency circuit that generates a stable latency signal in a high-speed semiconductor memory device, and a semiconductor memory device including the CAS latency circuit. The CAS latency circuit may include an internal read command signal generator and a latency clock generator coupled to a latency signal generator. In an embodiment of the invention, the latency signal generator outputs a stable latency signal by shifting an internal read signal output from the internal read command signal generator based on latency control clocks output from the latency clock generator.

摘要翻译： 本发明的实施例提供了一种在高速半导体存储器件中产生稳定等待时间信号的列地址选通（CAS）延迟电路，以及包括CAS等待电路的半导体存储器件。 CAS等待时间电路可以包括内部读命令信号发生器和耦合到等待时间信号发生器的等待时钟发生器。 在本发明的一个实施例中，等待时间信号发生器通过基于从等待时钟发生器输出的等待时间控制时钟移位从内部读取命令信号发生器输出的内部读取信号来输出稳定的等待时间信号。