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    Latency circuit using division method related to CAS latency and semiconductor memory device
    2.
    发明授权
    Latency circuit using division method related to CAS latency and semiconductor memory device 有权
    延迟电路采用与CAS延迟和半导体存储器件相关的划分方法

    公开(公告)号：US08045406B2

    公开(公告)日：2011-10-25

    申请号：US12697547

    申请日：2010-02-01

    申请人： Sang-hyuk Kwon ,  Byung-hoon Jeong

    发明人： Sang-hyuk Kwon ,  Byung-hoon Jeong

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C11/4076

    摘要： A latency circuit for use in a semiconductor memory device includes a latency control clock generator generating an m-divided division signal from an external clock and at least one latency control clock from the m-divided division signal, wherein m is a natural number greater than or equal to 2. The latency circuit also includes a latency signal generator generating a latency signal in response to the at least one latency control clock, a latency control signal and an internal read command signal, wherein the latency control signal is generated from a column address strobe (CAS) latency and the internal read command signal is generated in response to a received read command.

    摘要翻译： 用于半导体存储器件的等待时间电路包括等待时间控制时钟发生器，其产生来自外部时钟的m分割除法信号和来自m分割除法信号的至少一个等待时间控制时钟，其中m是大于 等待时间电路还包括响应于至少一个等待时间控制时钟产生等待时间信号的等待时间信号发生器，等待时间控制信号和内部读取命令信号，其中等待时间控制信号是从列产生的 地址选通（CAS）延迟和内部读命令信号是响应于接收到的读命令产生的。

    CAS latency circuit and semiconductor memory device including the same
    3.
    发明授权
    CAS latency circuit and semiconductor memory device including the same 有权
    CAS延迟电路和包括其的半导体存储器件

    公开(公告)号：US07675797B2

    公开(公告)日：2010-03-09

    申请号：US11928022

    申请日：2007-10-30

    申请人： Byung-hoon Jeong ,  Seung-bum Ko ,  Jeong-suk Yang

    发明人： Byung-hoon Jeong ,  Seung-bum Ko ,  Jeong-suk Yang

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C11/4076

    摘要： Embodiments of the invention provide a column address strobe (CAS) latency circuit that generates a stable latency signal in a high-speed semiconductor memory device, and a semiconductor memory device including the CAS latency circuit. The CAS latency circuit may include an internal read command signal generator and a latency clock generator coupled to a latency signal generator. In an embodiment of the invention, the latency signal generator outputs a stable latency signal by shifting an internal read signal output from the internal read command signal generator based on latency control clocks output from the latency clock generator.

    摘要翻译： 本发明的实施例提供了一种在高速半导体存储器件中产生稳定等待时间信号的列地址选通（CAS）延迟电路，以及包括CAS等待电路的半导体存储器件。 CAS等待时间电路可以包括内部读命令信号发生器和耦合到等待时间信号发生器的等待时钟发生器。 在本发明的一个实施例中，等待时间信号发生器通过基于从等待时钟发生器输出的等待时间控制时钟移位从内部读取命令信号发生器输出的内部读取信号来输出稳定的等待时间信号。

    Delay-locked loop, integrated circuit having the same, and method of driving the same
    4.
    发明授权
    Delay-locked loop, integrated circuit having the same, and method of driving the same 失效
    延迟锁定环，具有相同的集成电路及其驱动方法

    公开(公告)号：US07336559B2

    公开(公告)日：2008-02-26

    申请号：US11730793

    申请日：2007-04-04

    申请人： Byung-Hoon Jeong

    发明人： Byung-Hoon Jeong

    IPC分类号： G11C8/00 ,  G11C8/18 ,  H03L7/06 ,  H03K7/08

    CPC分类号： G11C29/028 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C29/02 ,  G11C29/50012

    摘要： A delay-locked loop (DLL) is disclosed with a phase detector configured to detect a phase difference between an external clock signal and an internal clock signal, a variable delay line configured to variably delay the external clock signal in relation to the phase difference to generate an intermediate clock signal, a selection unit configured to select between the intermediate clock signal and an inverted version of the intermediate clock signal in relation to an inversion control signal, and to generate an internal clock signal according to the selection, and an inversion determination unit configured to generate the inversion control signal in relation to transition of the external clock signal within a duty error margin.

    摘要翻译： 延迟锁定环（DLL）被公开，相位检测器被配置为检测外部时钟信号和内部时钟信号之间的相位差，可变延迟线被配置为相对于相位差可变地延迟外部时钟信号 产生中间时钟信号，选择单元，被配置为在中间时钟信号和中间时钟信号的反相版本之间相对于反相控制信号进行选择，并根据该选择产生内部时钟信号，并且反演确定 被配置为在占空比误差容限内产生与外部时钟信号的转变相关的反相控制信号。

    Latency circuit and semiconductor device comprising same
    6.
    发明授权
    Latency circuit and semiconductor device comprising same 有权
    延迟电路和包括该延迟电路的半导体器件

    公开(公告)号：US08437206B2

    公开(公告)日：2013-05-07

    申请号：US12857762

    申请日：2010-08-17

    申请人： In-Woo Jun ,  Byung Hoon Jeong ,  Min Soo Kim

    发明人： In-Woo Jun ,  Byung Hoon Jeong ,  Min Soo Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C7/227 ,  G11C8/18 ,  G11C2207/2272

    摘要： A latency circuit comprises a latency control block, an internal read command generator, and a latency signal generation unit. The latency control block generates a plurality of first control clocks by delaying a delay sync signal generated based on an external clock, and generates a second control clock having a margin with respect to a read command decoded based on the delay sync signal. The internal read command generator samples the second control clock using the decoded read command and generates an internal read command based on a sampled second control clock. The latency signal generation unit generates a latency signal based on a shifting operation performed on the internal read command using the plurality of first control clocks.

    摘要翻译： 延迟电路包括等待时间控制块，内部读命令发生器和等待时间信号生成单元。 等待时间控制块通过延迟基于外部时钟产生的延迟同步信号来产生多个第一控制时钟，并且生成相对于基于延迟同步信号解码的读命令具有余量的第二控制时钟。 内部读命令生成器使用解码读命令对第二控制时钟进行采样，并根据采样的第二控制时钟生成内部读指令。 等待时间信号生成单元基于使用多个第一控制时钟对内部读取命令执行的移位操作生成等待时间信号。

    Latency control circuit and method using queuing design method
    7.
    发明授权
    Latency control circuit and method using queuing design method 失效
    延迟控制电路和使用排队设计方法的方法

    公开(公告)号：US08230140B2

    公开(公告)日：2012-07-24

    申请号：US13178846

    申请日：2011-07-08

    申请人： Byung-Hoon Jeong ,  Hoe-Ju Chung

    发明人： Byung-Hoon Jeong ,  Hoe-Ju Chung

    IPC分类号： G06F3/00

    CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/109 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2272

    摘要： A latency control circuit includes a FIFO controller and a register unit. The FIFO controller may generate an increase signal according to an external command, and generate a decrease signal according to an internal command. The FIFO controller may also enable a depth point signal responsive to the increase signal and the decrease signal. The register unit may include n registers. The value n (rounded off) may be obtained by dividing a larger value of a maximum number of additive latencies and a maximum number of write latencies by a column cycle delay time (tCCD). The registers may store an address received with the external command responsive to the increase signal and a clock signal, and may shift either the address or a previous address to a neighboring register. The latency control circuit transmits an address stored in a register as a column address corresponding to the enabled depth point signal.

    摘要翻译： 等待时间控制电路包括FIFO控制器和寄存器单元。 FIFO控制器可以根据外部命令生成增加信号，并根据内部命令生成减少信号。 FIFO控制器还可以响应于增加信号和减小信号启用深度点信号。 寄存器单元可以包括n个寄存器。 值n（四舍五入）可以通过将最大数量的加性延迟和最大写入延迟数的较大值除以列周期延迟时间（tCCD）来获得。 寄存器可以响应于增加信号和时钟信号而存储与外部命令接收的地址，并且可以将地址或先前地址移位到相邻寄存器。 延迟控制电路将存储在寄存器中的地址作为与启用的深度点信号相对应的列地址。

    Clock signal generation circuit for reducuing current consumption, and semiconductor device having the same
    8.
    发明申请
    Clock signal generation circuit for reducuing current consumption, and semiconductor device having the same 有权
    用于减少电流消耗的时钟信号发生电路和具有相同功能的半导体器件

    公开(公告)号：US20100244915A1

    公开(公告)日：2010-09-30

    申请号：US12659881

    申请日：2010-03-24

    申请人： Sang-Hyuk Kwon ,  Byung Hoon Jeong ,  Jae Woong Lee

    发明人： Sang-Hyuk Kwon ,  Byung Hoon Jeong ,  Jae Woong Lee

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0812 ,  H03L7/07 ,  H03L7/0802

    摘要： In an example embodiment, the semiconductor device includes a clock signal generation circuit. The clock signal generation circuit is configured to generate at least one control clock signal in response to an external clock signal and a read command signal. The clock signal generation circuit includes a plurality of delay circuits, and the clock signal generation circuit is configured to selectively disable at least one of the plurality of delay circuits to reduce power consumption.

    摘要翻译： 在示例性实施例中，半导体器件包括时钟信号产生电路。 时钟信号生成电路被配置为响应于外部时钟信号和读取命令信号而生成至少一个控制时钟信号。 时钟信号生成电路包括多个延迟电路，并且时钟信号生成电路被配置为选择性地禁用多个延迟电路中的至少一个以减少功耗。

    LATENCY CIRCUIT USING DIVISION METHOD RELATED TO CAS LATENCY AND SEMICONDUCTOR MEMORY DEVICE
    9.
    发明申请
    LATENCY CIRCUIT USING DIVISION METHOD RELATED TO CAS LATENCY AND SEMICONDUCTOR MEMORY DEVICE 有权
    使用与CAS LATENCY和SEMICONDUCTOR MEMORY DEVICE相关的部分方法的延迟电路

    公开(公告)号：US20100128543A1

    公开(公告)日：2010-05-27

    申请号：US12697547

    申请日：2010-02-01

    申请人： Sang-hyuk KWON ,  Byung-hoon JEONG

    发明人： Sang-hyuk KWON ,  Byung-hoon JEONG

    IPC分类号： G11C7/00 ,  G11C8/18

    CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C11/4076

    摘要： A latency circuit for use in a semiconductor memory device includes a latency control clock generator generating an m-divided division signal from an external clock and at least one latency control clock from the m-divided division signal, wherein m is a natural number greater than or equal to 2. The latency circuit also includes a latency signal generator generating a latency signal in response to the at least one latency control clock, a latency control signal and an internal read command signal, wherein the latency control signal is generated from a column address strobe (CAS) latency and the internal read command signal is generated in response to a received read command.

    摘要翻译： 用于半导体存储器件的等待时间电路包括等待时间控制时钟发生器，其产生来自外部时钟的m分割除法信号和来自m分割除法信号的至少一个等待时间控制时钟，其中m是大于 等待时间电路还包括响应于至少一个等待时间控制时钟产生等待时间信号的等待时间信号发生器，等待时间控制信号和内部读取命令信号，其中等待时间控制信号是从列产生的 地址选通（CAS）延迟和内部读命令信号是响应于接收到的读命令产生的。

    CAS LATENCY CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
    10.
    发明申请
    CAS LATENCY CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
    CAS LATENCY电路和半导体存储器件，包括它们

    公开(公告)号：US20080101140A1

    公开(公告)日：2008-05-01

    申请号：US11928022

    申请日：2007-10-30

    申请人： Byung-hoon JEONG ,  Seung-bum KO ,  Jeong-suk YANG

    发明人： Byung-hoon JEONG ,  Seung-bum KO ,  Jeong-suk YANG

    IPC分类号： G11C8/18

    CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C11/4076

    摘要： Embodiments of the invention provide a column address strobe (CAS) latency circuit that generates a stable latency signal in a high-speed semiconductor memory device, and a semiconductor memory device including the CAS latency circuit. The CAS latency circuit may include an internal read command signal generator and a latency clock generator coupled to a latency signal generator. In an embodiment of the invention, the latency signal generator outputs a stable latency signal by shifting an internal read signal output from the internal read command signal generator based on latency control clocks output from the latency clock generator.

    摘要翻译： 本发明的实施例提供了一种在高速半导体存储器件中产生稳定等待时间信号的列地址选通（CAS）延迟电路，以及包括CAS等待电路的半导体存储器件。 CAS等待时间电路可以包括内部读命令信号发生器和耦合到等待时间信号发生器的等待时钟发生器。 在本发明的一个实施例中，等待时间信号发生器通过基于从等待时钟发生器输出的等待时间控制时钟移位从内部读取命令信号发生器输出的内部读取信号来输出稳定的等待时间信号。