公开(公告)号：US20100134331A1

公开(公告)日：2010-06-03

申请号：US12588926

申请日：2009-11-02

申请人： Martinus Cornelis Wezelenburg ,  Jeremy Piers Davies

发明人： Martinus Cornelis Wezelenburg ,  Jeremy Piers Davies

IPC分类号： H03M7/40

CPC分类号： H03M7/40

摘要： A data compressor for compressing a data signal and a corresponding data decompressor are disclosed. The data compressor comprises: compression circuitry for compressing said data signal using a plurality of variable length compression codes; a digital code select signal generator for generating a digital code select signal from an indicator signal indicative of a preferred compression distribution, a frequency of said digital code select signal being higher than a frequency of said indicator signal and an average value of said digital code select signal corresponding to an average value of said indicator signal; said compression circuitry being responsive to said digital code select signal to select between one of said plurality of compression codes in dependence upon a current value of said digital code select signal and to compress said data signal using said selected compression code.

摘要翻译： 公开了一种用于压缩数据信号的数据压缩器和相应的数据解压缩器。 数据压缩器包括：压缩电路，用于使用多个可变长度压缩码压缩所述数据信号; 数字码选择信号发生器，用于从表示优选压缩分布的指示信号产生数字码选择信号，所述数字码选择信号的频率高于所述指示信号的频率，所述数字码选择的平均值 信号对应于所述指示信号的平均值; 所述压缩电路响应于所述数字代码选择信号，以根据所述数字代码选择信号的当前值来选择所述多个压缩代码之一，并使用所选择的压缩代码压缩所述数据信号。

公开(公告)号：US20100005269A1

公开(公告)日：2010-01-07

申请号：US12216253

申请日：2008-07-01

申请人： Jeremy Piers Davies ,  David Hennah Mansell ,  Richard Roy Grisenthwaite

发明人： Jeremy Piers Davies ,  David Hennah Mansell ,  Richard Roy Grisenthwaite

IPC分类号： G06F12/02

CPC分类号： G06F12/126 ,  G06F12/1036

摘要： Address translation circuitry for translating virtual addresses to physical addresses for a data processor in response to access requests from said data processor targeting virtual addresses is disclosed. The address translation circuitry comprises: a data store comprising a plurality of entries for storing a plurality of mappings of ranges of virtual addresses to ranges of physical addresses for said data processor and additional data associated with each of said plurality of mappings within a table; updating circuitry for updating said table in response to an access request for a virtual address that is not mapped by said table, said updating circuitry being responsive to receipt of a mapping for said virtual address to: select a plurality of entries in said table suitable for storing said received mapping; and determine one of said plurality of selected entries to be overwritten by said received mapping in dependence upon at least a portion of said additional data stored in said one of said plurality of selected entries.

摘要翻译： 公开了用于将数据处理器的虚拟地址转换为物理地址的地址转换电路，以响应来自所述数据处理器的虚拟地址的访问请求。 地址转换电路包括：数据存储器，包括多个条目，用于存储虚拟地址范围的多个映射到所述数据处理器的物理地址范围和与表内的所述多个映射中的每一个相关联的附加数据; 更新电路，用于响应于未被所述表映射的虚拟地址的访问请求来更新所述表，所述更新电路响应于接收到所述虚拟地址的映射，以选择在所述表中适合的多个条目 存储所述接收的映射; 并且根据存储在所述多个选择的条目中的所述一个中的所述附加数据的至少一部分，确定要被所述接收的映射覆盖的所述多个所选择的条目中的一个。

公开(公告)号：US08051271B2

公开(公告)日：2011-11-01

申请号：US12216253

申请日：2008-07-01

申请人： Jeremy Piers Davies ,  David Hennah Mansell ,  Richard Roy Grisenthwaite

发明人： Jeremy Piers Davies ,  David Hennah Mansell ,  Richard Roy Grisenthwaite

IPC分类号： G06F12/02

CPC分类号： G06F12/126 ,  G06F12/1036

摘要： Address translation circuitry for translating virtual addresses to physical addresses for a data processor in response to access requests from said data processor targeting virtual addresses is disclosed. The address translation circuitry comprises: a data store comprising a plurality of entries for storing a plurality of mappings of ranges of virtual addresses to ranges of physical addresses for said data processor and additional data associated with each of said plurality of mappings within a table; updating circuitry for updating said table in response to an access request for a virtual address that is not mapped by said table, said updating circuitry being responsive to receipt of a mapping for said virtual address to: select a plurality of entries in said table suitable for storing said received mapping; and determine one of said plurality of selected entries to be overwritten by said received mapping in dependence upon at least a portion of said additional data stored in said one of said plurality of selected entries.

摘要翻译： 公开了用于将数据处理器的虚拟地址转换为物理地址的地址转换电路，以响应来自所述数据处理器的虚拟地址的访问请求。 地址转换电路包括：数据存储器，包括多个条目，用于存储虚拟地址范围的多个映射到所述数据处理器的物理地址范围和与表内的所述多个映射中的每一个相关联的附加数据; 更新电路，用于响应于未被所述表映射的虚拟地址的访问请求来更新所述表，所述更新电路响应于接收到所述虚拟地址的映射，以选择在所述表中适合的多个条目 存储所述接收的映射; 并且根据存储在所述多个选择的条目中的所述一个中的所述附加数据的至少一部分，确定要被所述接收的映射覆盖的所述多个所选择的条目中的一个。

公开(公告)号：US07249270B2

公开(公告)日：2007-07-24

申请号：US11044261

申请日：2005-01-28

申请人： David Hennah Mansell ,  Richard Roy Grisenthwaite ,  Harry Samuel Thomas Fearnhamm ,  Jeremy Piers Davies

发明人： David Hennah Mansell ,  Richard Roy Grisenthwaite ,  Harry Samuel Thomas Fearnhamm ,  Jeremy Piers Davies

IPC分类号： G06F1/32 ,  G06F12/00

CPC分类号： G06F13/24 ,  G06F1/3228

摘要： The present invention provides a data processing apparatus and method of controlling access to a shared resource. The data processing apparatus has a plurality of processors operable to perform respective data processing operations requiring access to the shared resource, and a path is provided interconnecting the plurality of processors. An access control mechanism is operable to control access to the shared resource by the plurality of processors, each processor being operable to enter a power saving mode if access to the shared resource is required but the access control mechanism is preventing access to the shared resource by that processor. Further, each processor is operable, when that processor has access to the shared resource, to issue a notification on the path when access to the shared resource is no longer required by that processor. A processor in the power saving mode is arranged, upon receipt of that notification, to exit the power saving mode and to seek access to the shared resource. This approach has been found to result in significant power savings.

摘要翻译： 本发明提供一种控制对共享资源的访问的数据处理装置和方法。 数据处理装置具有可操作以执行需要访问共享资源的相应数据处理操作的多个处理器，并且提供互连多个处理器的路径。 访问控制机制可操作以控制多个处理器对共享资源的访问，如果需要对共享资源的访问，则每个处理器可操作以进入省电模式，但是访问控制机制阻止对共享资源的访问 那个处理器。 此外，当处理器具有对共享资源的访问时，每个处理器可操作地在该处理器不再需要对共享资源的访问时在路径上发布通知。 处于省电模式的处理器在接收到该通知时被布置为退出省电模式并寻求对共享资源的访问。 已经发现这种方法导致显着的功率节省。

公开(公告)号：US07936290B2

公开(公告)日：2011-05-03

申请号：US12588926

申请日：2009-11-02

申请人： Martinus Cornelis Wezelenburg ,  Jeremy Piers Davies

发明人： Martinus Cornelis Wezelenburg ,  Jeremy Piers Davies

IPC分类号： H03M7/40

CPC分类号： H03M7/40

摘要： A data compressor for compressing a data signal and a corresponding data decompressor are disclosed. The data compressor comprises: compression circuitry for compressing said data signal using a plurality of variable length compression codes; a digital code select signal generator for generating a digital code select signal from an indicator signal indicative of a preferred compression distribution, a frequency of said digital code select signal being higher than a frequency of said indicator signal and an average value of said digital code select signal corresponding to an average value of said indicator signal; said compression circuitry being responsive to said digital code select signal to select between one of said plurality of compression codes in dependence upon a current value of said digital code select signal and to compress said data signal using said selected compression code.

摘要翻译： 公开了一种用于压缩数据信号的数据压缩器和相应的数据解压缩器。 数据压缩器包括：压缩电路，用于使用多个可变长度压缩码压缩所述数据信号; 数字码选择信号发生器，用于从表示优选压缩分布的指示信号产生数字码选择信号，所述数字码选择信号的频率高于所述指示信号的频率，所述数字码选择的平均值 信号对应于所述指示信号的平均值; 所述压缩电路响应于所述数字代码选择信号，以根据所述数字代码选择信号的当前值来选择所述多个压缩代码之一，并使用所选择的压缩代码压缩所述数据信号。