公开(公告)号：US07249270B2

公开(公告)日：2007-07-24

申请号：US11044261

申请日：2005-01-28

申请人： David Hennah Mansell ,  Richard Roy Grisenthwaite ,  Harry Samuel Thomas Fearnhamm ,  Jeremy Piers Davies

发明人： David Hennah Mansell ,  Richard Roy Grisenthwaite ,  Harry Samuel Thomas Fearnhamm ,  Jeremy Piers Davies

IPC分类号： G06F1/32 ,  G06F12/00

CPC分类号： G06F13/24 ,  G06F1/3228

摘要： The present invention provides a data processing apparatus and method of controlling access to a shared resource. The data processing apparatus has a plurality of processors operable to perform respective data processing operations requiring access to the shared resource, and a path is provided interconnecting the plurality of processors. An access control mechanism is operable to control access to the shared resource by the plurality of processors, each processor being operable to enter a power saving mode if access to the shared resource is required but the access control mechanism is preventing access to the shared resource by that processor. Further, each processor is operable, when that processor has access to the shared resource, to issue a notification on the path when access to the shared resource is no longer required by that processor. A processor in the power saving mode is arranged, upon receipt of that notification, to exit the power saving mode and to seek access to the shared resource. This approach has been found to result in significant power savings.

摘要翻译： 本发明提供一种控制对共享资源的访问的数据处理装置和方法。 数据处理装置具有可操作以执行需要访问共享资源的相应数据处理操作的多个处理器，并且提供互连多个处理器的路径。 访问控制机制可操作以控制多个处理器对共享资源的访问，如果需要对共享资源的访问，则每个处理器可操作以进入省电模式，但是访问控制机制阻止对共享资源的访问 那个处理器。 此外，当处理器具有对共享资源的访问时，每个处理器可操作地在该处理器不再需要对共享资源的访问时在路径上发布通知。 处于省电模式的处理器在接收到该通知时被布置为退出省电模式并寻求对共享资源的访问。 已经发现这种方法导致显着的功率节省。

公开(公告)号：US08051271B2

公开(公告)日：2011-11-01

申请号：US12216253

申请日：2008-07-01

申请人： Jeremy Piers Davies ,  David Hennah Mansell ,  Richard Roy Grisenthwaite

发明人： Jeremy Piers Davies ,  David Hennah Mansell ,  Richard Roy Grisenthwaite

IPC分类号： G06F12/02

CPC分类号： G06F12/126 ,  G06F12/1036

摘要： Address translation circuitry for translating virtual addresses to physical addresses for a data processor in response to access requests from said data processor targeting virtual addresses is disclosed. The address translation circuitry comprises: a data store comprising a plurality of entries for storing a plurality of mappings of ranges of virtual addresses to ranges of physical addresses for said data processor and additional data associated with each of said plurality of mappings within a table; updating circuitry for updating said table in response to an access request for a virtual address that is not mapped by said table, said updating circuitry being responsive to receipt of a mapping for said virtual address to: select a plurality of entries in said table suitable for storing said received mapping; and determine one of said plurality of selected entries to be overwritten by said received mapping in dependence upon at least a portion of said additional data stored in said one of said plurality of selected entries.

摘要翻译： 公开了用于将数据处理器的虚拟地址转换为物理地址的地址转换电路，以响应来自所述数据处理器的虚拟地址的访问请求。 地址转换电路包括：数据存储器，包括多个条目，用于存储虚拟地址范围的多个映射到所述数据处理器的物理地址范围和与表内的所述多个映射中的每一个相关联的附加数据; 更新电路，用于响应于未被所述表映射的虚拟地址的访问请求来更新所述表，所述更新电路响应于接收到所述虚拟地址的映射，以选择在所述表中适合的多个条目 存储所述接收的映射; 并且根据存储在所述多个选择的条目中的所述一个中的所述附加数据的至少一部分，确定要被所述接收的映射覆盖的所述多个所选择的条目中的一个。

公开(公告)号：US20100005269A1

公开(公告)日：2010-01-07

申请号：US12216253

申请日：2008-07-01

申请人： Jeremy Piers Davies ,  David Hennah Mansell ,  Richard Roy Grisenthwaite

发明人： Jeremy Piers Davies ,  David Hennah Mansell ,  Richard Roy Grisenthwaite

IPC分类号： G06F12/02

CPC分类号： G06F12/126 ,  G06F12/1036

摘要： Address translation circuitry for translating virtual addresses to physical addresses for a data processor in response to access requests from said data processor targeting virtual addresses is disclosed. The address translation circuitry comprises: a data store comprising a plurality of entries for storing a plurality of mappings of ranges of virtual addresses to ranges of physical addresses for said data processor and additional data associated with each of said plurality of mappings within a table; updating circuitry for updating said table in response to an access request for a virtual address that is not mapped by said table, said updating circuitry being responsive to receipt of a mapping for said virtual address to: select a plurality of entries in said table suitable for storing said received mapping; and determine one of said plurality of selected entries to be overwritten by said received mapping in dependence upon at least a portion of said additional data stored in said one of said plurality of selected entries.

摘要翻译： 公开了用于将数据处理器的虚拟地址转换为物理地址的地址转换电路，以响应来自所述数据处理器的虚拟地址的访问请求。 地址转换电路包括：数据存储器，包括多个条目，用于存储虚拟地址范围的多个映射到所述数据处理器的物理地址范围和与表内的所述多个映射中的每一个相关联的附加数据; 更新电路，用于响应于未被所述表映射的虚拟地址的访问请求来更新所述表，所述更新电路响应于接收到所述虚拟地址的映射，以选择在所述表中适合的多个条目 存储所述接收的映射; 并且根据存储在所述多个选择的条目中的所述一个中的所述附加数据的至少一部分，确定要被所述接收的映射覆盖的所述多个所选择的条目中的一个。

公开(公告)号：US20100235579A1

公开(公告)日：2010-09-16

申请号：US12223173

申请日：2006-09-18

申请人： Stuart David Biles ,  Richard Roy Grisenthwaite ,  David Hennah Mansell

发明人： Stuart David Biles ,  Richard Roy Grisenthwaite ,  David Hennah Mansell

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/127 ,  G06F12/0862

摘要： A data processing apparatus, and method of managing at least one cache within such an apparatus, are provided. The data processing apparatus has at least one processing unit for executing a sequence of instructions, with each such processing unit having a cache associated therewith, each cache having a plurality of cache lines for storing data values for access by the associated processing unit when executing the sequence of instructions. Identification logic is provided which, for each cache, monitors data traffic within the data processing apparatus and based thereon generates a preferred for eviction identification identifying one or more of the data values as preferred for eviction. Cache maintenance logic is then arranged, for each cache, to implement a cache maintenance operation during which selection of one or more data values for eviction from that cache is performed having regard to any preferred for eviction identification generated by the identification logic for data values stored in that cache. It has been found that such an approach provides a very flexible technique for seeking to improve cache storage utilisation.

摘要翻译： 提供了一种数据处理装置以及管理这种装置中的至少一个高速缓存的方法。 数据处理装置具有用于执行指令序列的至少一个处理单元，每个这样的处理单元具有与其相关联的高速缓冲存储器，每个高速缓冲存储器具有多个高速缓存行，用于存储由相关联的处理单元执行访问时的数据值 指令序列 提供了识别逻辑，对于每个高速缓存来说，监视数据处理装置内的数据业务，并且基于此，生成用于驱逐的标识的优选，以便识别为驱逐优选的一个或多个数据值。 然后，对于每个高速缓存，缓存维护逻辑被设置为实现高速缓存维护操作，在该高速缓存维护操作期间，考虑到存储的数据值的识别逻辑生成的用于逐出识别​​的任何优选的执行，从该高速缓存中选择一个或多个数据值 在那个缓存中。 已经发现，这种方法为寻求提高缓存存储利用率提供了非常灵活的技术。

公开(公告)号：US20090222816A1

公开(公告)日：2009-09-03

申请号：US12379082

申请日：2009-02-12

申请人： David Hennah Mansell ,  Richard Roy Grisenthwaite ,  Stuart David Biles

发明人： David Hennah Mansell ,  Richard Roy Grisenthwaite ,  Stuart David Biles

IPC分类号： G06F9/455

CPC分类号： G06F12/145

摘要： A data processing apparatus and method are provided for controlling access to secure memory by virtual machines executing on processing circuitry. The processing circuitry executes hypervisor software to support the execution of multiple virtual machines on the processing circuitry. A memory system is provided for storing data for access by the processing circuitry, the memory system comprising secure memory for storing secure data and non-secure memory for storing non-secure data, the secure memory only being accessible via a secure access request. Address translation circuitry is responsive to an access request issued by a current virtual machine specifying a virtual address, to perform an address translation process to identify a physical address in the memory, and to cause a modified access request to be issued to the memory system specifying the physical address. A trusted virtual machine identifier is maintained and managed by the hypervisor software, with the hypervisor software setting the trusted virtual machine identifier if the current virtual machine is to be trusted to access the secure memory. Accordingly, in response to the access request issued by the current virtual machine, the address translation circuitry is only able to cause the modified access request to be issued as a secure access request specifying a physical address within the secure memory if the trusted virtual machine identifier is set. By such an approach, the hypervisor software is able to support multiple virtual machines at least some of which have access to secure memory under conditions controlled by the hypervisor software.

摘要翻译： 提供了一种数据处理装置和方法，用于通过在处理电路上执行的虚拟机来控制对安全存储器的访问。 处理电路执行管理程序软件以支持处理电路上的多个虚拟机的执行。 提供了一种用于存储由处理电路进行访问的数据的存储器系统，该存储器系统包括用于存储安全数据的安全存储器和用于存储非安全数据的非安全存储器，该安全存储器仅可通过安全访问请求访问。 地址转换电路响应于指定虚拟地址的当前虚拟机发出的访问请求，执行地址转换处理以识别存储器中的物理地址，并且将经修改的访问请求发布到存储器系统指定 物理地址。 由管理程序软件维护和管理可信赖的虚拟机标识符，如果当前虚拟机被信任以访问安全存储器，则管理程序软件设置可信虚拟机标识符。 因此，响应于当前虚拟机发出的访问请求，地址转换电路仅能够将修改的访问请求作为指定安全存储器内的物理地址的安全访问请求发出，如果可信虚拟机标识符 被设置。 通过这种方法，管理程序软件能够支持多个虚拟机，其中至少一些虚拟机在由管理程序软件控制的条件下可以访问安全存储器。

公开(公告)号：US20070143515A1

公开(公告)日：2007-06-21

申请号：US11603091

申请日：2006-11-22

申请人： Daniel Kershaw ,  Richard Roy Grisenthwaite ,  Stuart David Biles ,  David Hennah Mansell

发明人： Daniel Kershaw ,  Richard Roy Grisenthwaite ,  Stuart David Biles ,  David Hennah Mansell

IPC分类号： G06F13/26

CPC分类号： G06F21/52 ,  G06F13/26

摘要： An interrupt controller 2 is provided with priority registers 6 storing priority values P0-P9 used to determine prioritisation between received interrupt signals I0-I9. A priority value accessing circuit 10 provides multiple mappings to the priority values stored in dependence upon the priority value manager 16, 18, seeking to make an access. In this way, a first priority value manager 18, such as a secure operating system, can be given exclusive access to the highest priority values whilst a second priority value manager 16, such as a non-secure operating system, can be given access to a range of priority values as stored which are of a lower priority and yet as written or read by the non-secure operating system appear to the non-secure operating system to have a different, such as higher, priority level.

摘要翻译： 中断控制器2设置有优先级寄存器6，优先级寄存器6存储优先级值P 0 -P 9，用于确定接收到的中断信号I 0至I 9之间的优先级。 优先级值访问电路10根据优先权值管理器16,18存储的优先权值提供多个映射，寻求进行访问。 以这种方式，诸如安全操作系统的第一优先级值管理器18可以被授予对最高优先级值的排他访问，而可以给予诸如非安全操作系统的第二优先级值管理器16访问 所存储的优先级较低的范围的优先权较低，但由非安全操作系统写入或读取，对于非安全操作系统来说，具有不同的，例如较高的优先级。

公开(公告)号：US08418175B2

公开(公告)日：2013-04-09

申请号：US12379082

申请日：2009-02-12

申请人： David Hennah Mansell ,  Richard Roy Grisenthwaite ,  Stuart David Biles

发明人： David Hennah Mansell ,  Richard Roy Grisenthwaite ,  Stuart David Biles

IPC分类号： G06F9/00

CPC分类号： G06F12/145

摘要： Processing circuitry executes hypervisor software to support the execution of multiple virtual machines on the processing circuitry. A memory system stores data for access by the processing circuitry and includes secure memory and non-secure memory . The secure memory is only accessible via a secure access request. Address translation circuitry is responsive to an access request issued by a current virtual machine specifying a virtual address, to perform an address translation process to identify a physical address in the memory, and to cause a modified access request to be issued to the memory system specifying the physical address. The hypervisor software sets a trusted virtual machine identifier if the current virtual machine is to be trusted to access the secure memory. The address translation circuitry can only cause the modified access request to be issued as a secure access request to the secure memory if the trusted identifier is set.

摘要翻译： 处理电路执行管理程序软件以支持在处理电路上执行多个虚拟机。 存储器系统存储用于由处理电路访问的数据，并且包括安全存储器和非安全存储器。 安全存储器只能通过安全访问请求访问。 地址转换电路响应于指定虚拟地址的当前虚拟机发出的访问请求，执行地址转换处理以识别存储器中的物理地址，并且将经修改的访问请求发布到存储器系统指定 物理地址。 如果当前虚拟机被信任以访问安全存储器，则管理程序软件设置可信赖的虚拟机标识符。 如果设置了可信标识符，则地址转换电路只能使经修改的访问请求作为对安全存储器的安全访问请求发出。

公开(公告)号：US08041897B2

公开(公告)日：2011-10-18

申请号：US12223173

申请日：2006-09-18

申请人： Stuart David Biles ,  Richard Roy Grisenthwaite ,  David Hennah Mansell

发明人： Stuart David Biles ,  Richard Roy Grisenthwaite ,  David Hennah Mansell

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/127 ,  G06F12/0862

摘要： A data processing apparatus, and method of managing at least one cache within such an apparatus, are provided. The data processing apparatus has at least one processing unit for executing a sequence of instructions, with each such processing unit having a cache associated therewith, each cache having a plurality of cache lines for storing data values for access by the associated processing unit when executing the sequence of instructions. Identification logic is provided which, for each cache, monitors data traffic within the data processing apparatus and based thereon generates a preferred for eviction identification identifying one or more of the data values as preferred for eviction. Cache maintenance logic is then arranged, for each cache, to implement a cache maintenance operation during which selection of one or more data values for eviction from that cache is performed having regard to any preferred for eviction identification generated by the identification logic for data values stored in that cache. It has been found that such an approach provides a very flexible technique for seeking to improve cache storage utilisation.

摘要翻译： 提供了一种数据处理装置以及管理这种装置中的至少一个高速缓存的方法。 数据处理装置具有用于执行指令序列的至少一个处理单元，每个这样的处理单元具有与其相关联的高速缓存，每个高速缓冲存储器具有多个高速缓存行，用于存储由相关处理单元执行访问时的数据值 指令序列 提供了识别逻辑，对于每个高速缓存来说，监视数据处理装置内的数据业务，并且基于此，生成用于驱逐的标识的优选，以便识别为驱逐优选的一个或多个数据值。 然后，对于每个高速缓存，缓存维护逻辑被布置以实现高速缓存维护操作，在该高速缓存维护操作期间，考虑到存储的数据值的识别逻辑生成的用于逐出识别​​的任何优选的执行，从该缓存中选择一个或多个用于逐出的数据值 在那个缓存中。 已经发现，这种方法为寻求提高缓存存储利用率提供了非常灵活的技术。

公开(公告)号：US20100094613A1

公开(公告)日：2010-04-15

申请号：US12453806

申请日：2009-05-22

申请人： Stewart David Biles ,  David Hennah Mansell ,  Richard Roy Grisenthwaite

发明人： Stewart David Biles ,  David Hennah Mansell ,  Richard Roy Grisenthwaite

IPC分类号： G06F9/455 ,  G06F12/00

CPC分类号： G06F9/45558 ,  G06F2009/45583

摘要： A data processing apparatus 12 is provided with a memory management unit 24 which triggers memory aborts. When a memory abort occurs, data characterising the memory abort is written to a fault status register 28 (memory-abort register). The data characterising the memory abort includes data identifying a register number associated with the memory access which gave rise to the memory abort. This register identifying data is used to emulate the action of the memory access instruction without having to read the program instruction lead to the memory abort. This is useful in providing virtualisation support for a virtual data processing apparatus 2.

摘要翻译： 数据处理装置12设置有触发存储器中止的存储器管理单元24。 当发生存储器中止时，表征存储器中止的数据被写入故障状态寄存器28（存储器中止寄存器）。 表征存储器中止的数据包括识别与存储器访问相关联的寄存器号的数据，这导致存储器中止。 该寄存器识别数据用于模拟存储器访问指令的动作，而不必读取导致存储器中止的程序指令。 这在为虚拟数据处理设备2提供虚拟化支持方面是有用的。

公开(公告)号：US08140820B2

公开(公告)日：2012-03-20

申请号：US12153617

申请日：2008-05-21

申请人： David Hennah Mansell ,  Richard Roy Grisenthwaite

发明人： David Hennah Mansell ,  Richard Roy Grisenthwaite

IPC分类号： G06F12/10

CPC分类号： G06F12/1009 ,  G06F12/1036

摘要： A data processing apparatus has address translation circuitry which is responsive to an access request specifying a virtual address, to perform a multi-stage address translation process to produce, via at least one intermediate address, a physical address in memory corresponding to the virtual address. The address translation circuitry references a storage unit, with each entry of the storage unit storing address translation information for one or more virtual addresses. Each entry has a field indicating whether the address translation information is consolidated address translation information or partial address translation information. If when processing an access request, it is determined that the relevant entry in the storage unit provides consolidated address translation information, the address translation circuitry produces a physical address directly from the consolidated address translation information. If on the other hand the relevant entry stores partial address translation information, the address translation circuitry produces an intermediate address from the partial address translation information and then performs the remainder of the multi-stage address translation process. Such an approach provides the performance benefits associated with a consolidated entry mechanism within the storage unit, while also allowing certain problem cases to be handled correctly and in an efficient manner.

摘要翻译： 数据处理装置具有响应于指定虚拟地址的访问请求的地址转换电路，以执行多级地址转换处理，以通过至少一个中间地址产生与虚拟地址相对应的存储器中的物理地址。 地址转换电路参考存储单元，存储单元的每个条目存储一个或多个虚拟地址的地址转换信息。 每个条目具有指示地址转换信息是合并地址转换信息还是部分地址转换信息的字段。 如果当处理访问请求时，确定存储单元中的相关条目提供合并的地址转换信息，地址转换电路直接从合并地址转换信息产生物理地址。 如果相关条目存储部分地址转换信息，则地址转换电路从部分地址转换信息产生中间地址，然后执行多级地址转换处理的剩余部分。 这种方法提供了与存储单元内的综合进入机制相关联的性能优点，同时还允许以有效的方式正确地处理某些问题情况。