公开(公告)号：US08294149B2

公开(公告)日：2012-10-23

申请号：US11935724

申请日：2007-11-06

申请人： Kerry Bernstein ,  Jerome L. Cann ,  Christopher M. Durham ,  Paul D. Kartschoke ,  Peter J. Klim ,  Donald L. Wheater

发明人： Kerry Bernstein ,  Jerome L. Cann ,  Christopher M. Durham ,  Paul D. Kartschoke ,  Peter J. Klim ,  Donald L. Wheater

IPC分类号： H01L23/58

CPC分类号： H01L22/32 ,  H01L21/4846 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/6835 ,  H01L2224/13005 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079

摘要： A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.

摘要翻译： 在外围测试结构衬底内形成通孔的多个外围测试结构衬底（PTSS）。 周边测试结构层和至少一个功能层通过通孔形成在多个PTSS的一侧上。 多个PTSS通孔中的另一侧在外围测试结构层和至少一个功能层的制造过程中暴露出来，以提供用于在整个制造顺序中测试各个层的功能性的接入点。 可以在完成所有至少一个功能层的所有制造之后执行C4键合。 不需要3D组装载体或C4载体衬底，因为外围测试结构衬底具有足够的机械强度以支撑外围测试结构层和至少一个功能层。

公开(公告)号：US07230335B2

公开(公告)日：2007-06-12

申请号：US10711765

申请日：2004-10-04

申请人： Jerome L. Cann ,  Steven J. Holmes ,  Leendert M. Huisman ,  Cherie R. Kagan ,  Leah M. Pastel ,  Paul W. Pastel ,  James R. Salimeno, III ,  David P. Vallett

发明人： Jerome L. Cann ,  Steven J. Holmes ,  Leendert M. Huisman ,  Cherie R. Kagan ,  Leah M. Pastel ,  Paul W. Pastel ,  James R. Salimeno, III ,  David P. Vallett

IPC分类号： H01L23/48 ,  H01L21/302

CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/7688

摘要： The present invention provides inspection methods and structures for facilitating the visualization and/or detection of specific chip structures. Optical or fluorescent labeling techniques are used to “stain” a specific chip structure for easier detection of the structure. Also, a temporary/sacrificial illuminating (e.g., fluorescent) film is added to the semiconductor process to facilitate the detection of a specific chip structure. Further, a specific chip structure is doped with a fluorescent material during the semiconductor process. A method of the present invention comprises: providing a first and a second material; processing the first material to form a portion of a semiconductor structure; and detecting a condition of the second material to determine whether processing of the first material is complete.

摘要翻译： 本发明提供了用于促进特定芯片结构的可视化和/或检测的检查方法和结构。 光学或荧光标记技术用于“污染”特定的芯片结构，以便于检测结构。 此外，向半导体工艺中添加临时/牺牲照明（例如荧光）膜以便于检测特定的芯片结构。 此外，在半导体工艺期间，用荧光材料掺杂特定的芯片结构。 本发明的方法包括：提供第一和第二材料; 处理所述第一材料以形成半导体结构的一部分; 以及检测所述第二材料的状态以确定所述第一材料的处理是否完成。

公开(公告)号：US08729549B2

公开(公告)日：2014-05-20

申请号：US13533191

申请日：2012-06-26

申请人： Kerry Bernstein ,  Jerome L. Cann ,  Christopher M. Durham ,  Paul D. Kartschoke ,  Peter J. Klim ,  Donald L. Wheater

发明人： Kerry Bernstein ,  Jerome L. Cann ,  Christopher M. Durham ,  Paul D. Kartschoke ,  Peter J. Klim ,  Donald L. Wheater

IPC分类号： H01L23/58

CPC分类号： H01L22/32 ,  H01L21/4846 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/6835 ,  H01L2224/13005 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079

摘要： A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.

摘要翻译： 在外围测试结构衬底内形成通孔的多个外围测试结构衬底（PTSS）。 周边测试结构层和至少一个功能层通过通孔形成在多个PTSS的一侧上。 多个PTSS通孔中的另一侧在外围测试结构层和至少一个功能层的制造过程中暴露出来，以提供用于在整个制造顺序中测试各个层的功能性的接入点。 可以在完成所有至少一个功能层的所有制造之后执行C4键合。 不需要3D组装载体或C4载体衬底，因为外围测试结构衬底具有足够的机械强度以支撑外围测试结构层和至少一个功能层。

公开(公告)号：US20120264241A1

公开(公告)日：2012-10-18

申请号：US13533188

申请日：2012-06-26

申请人： Kerry Bernstein ,  Jerome L. Cann ,  Christopher M. Durham ,  Paul D. Kartschoke ,  Peter J. Klim ,  Donald L. Wheater

发明人： Kerry Bernstein ,  Jerome L. Cann ,  Christopher M. Durham ,  Paul D. Kartschoke ,  Peter J. Klim ,  Donald L. Wheater

IPC分类号： H01L21/66

CPC分类号： H01L22/32 ,  H01L21/4846 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/6835 ,  H01L2224/13005 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079

摘要： A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.

摘要翻译： 在外围测试结构衬底内形成通孔的多个外围测试结构衬底（PTSS）。 周边测试结构层和至少一个功能层通过通孔形成在多个PTSS的一侧上。 多个PTSS通孔中的另一侧在外围测试结构层和至少一个功能层的制造过程中暴露出来，以提供用于在整个制造顺序中测试各个层的功能性的接入点。 可以在完成所有至少一个功能层的所有制造之后执行C4键合。 不需要3D组装载体或C4载体衬底，因为外围测试结构衬底具有足够的机械强度以支撑外围测试结构层和至少一个功能层。

公开(公告)号：US20090114913A1

公开(公告)日：2009-05-07

申请号：US11935724

申请日：2007-11-06

申请人： Kerry Bernstein ,  Jerome L. Cann ,  Christopher M. Durham ,  Paul D. Kartschoke ,  Peter J. Klim ,  Donald L. Wheater

发明人： Kerry Bernstein ,  Jerome L. Cann ,  Christopher M. Durham ,  Paul D. Kartschoke ,  Peter J. Klim ,  Donald L. Wheater

IPC分类号： H01L23/58 ,  H01L21/66

CPC分类号： H01L22/32 ,  H01L21/4846 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/6835 ,  H01L2224/13005 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079

摘要： A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.

摘要翻译： 在外围测试结构衬底内形成通孔的多个外围测试结构衬底（PTSS）。 周边测试结构层和至少一个功能层通过通孔形成在多个PTSS的一侧上。 多个PTSS通孔中的另一侧在外围测试结构层和至少一个功能层的制造过程中暴露出来，以提供用于在整个制造顺序中测试各个层的功能性的接入点。 可以在完成所有至少一个功能层的所有制造之后执行C4键合。 不需要3D组装载体或C4载体衬底，因为外围测试结构衬底具有足够的机械强度以支撑外围测试结构层和至少一个功能层。

公开(公告)号：US20120262197A1

公开(公告)日：2012-10-18

申请号：US13533191

申请日：2012-06-26

申请人： Kerry Bernstein ,  Jerome L. Cann ,  Christopher M. Durham ,  Paul D. Kartschoke ,  Peter J. Klim ,  Donald L. Wheater

发明人： Kerry Bernstein ,  Jerome L. Cann ,  Christopher M. Durham ,  Paul D. Kartschoke ,  Peter J. Klim ,  Donald L. Wheater

IPC分类号： G01R31/3187 ,  G01R1/067 ,  G01R31/00 ,  G01R31/02

CPC分类号： H01L22/32 ,  H01L21/4846 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/6835 ,  H01L2224/13005 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079

摘要： A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.