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    High performance, low power, dynamically latched up/down counter
    2.
    发明授权
    High performance, low power, dynamically latched up/down counter 失效
    高性能，低功耗，动态锁存上/下计数器

    公开(公告)号：US07587020B2

    公开(公告)日：2009-09-08

    申请号：US11739756

    申请日：2007-04-25

    申请人： Jethro C. Law ,  Trong V. Luong ,  Hung C. Ngo ,  Peter J. Klim

    发明人： Jethro C. Law ,  Trong V. Luong ,  Hung C. Ngo ,  Peter J. Klim

    IPC分类号： H03K25/00 ,  H03K23/50

    CPC分类号： H03K23/40 ,  H03K21/026

    摘要： A high performance, low power up/down counter is set forth. The counter presented is controlled by two clock pulses, an up pulse and a down pulse, and updates all bits of the counter in parallel. These bits are then latched using a scannable pulsed limited output switching dynamic logic latch. By using a limited switch dynamic logic latch, the counter is able to utilize the speed of dynamic logic without requiring the traditional dynamic logic power. The area saved and speed gained by using a dynamic latch is significant compared to a typical edge-triggered flip-flop. Additionally, by computing all the next count state bits in parallel, the counter reduces an overall count computation delay by eliminating the counter ripple.

    摘要翻译： 提出了一个高性能，低功耗的上/下计数器。 提供的计数器由两个时钟脉冲，上升脉冲和下降脉冲控制，并并行更新计数器的所有位。 然后使用可扫描的脉冲限制输出开关动态逻辑锁存器锁存这些位。 通过使用有限开关动态逻辑锁存器，计数器能够利用动态逻辑的速度，而不需要传统的动态逻辑电源。 与典型的边沿触发触发器相比，通过使用动态锁存器保存的区域和速度是显着的。 此外，通过并行计算所有下一个计数状态位，计数器通过消除计数器纹波来减少总计数计算延迟。

    METHOD AND APPARATUS FOR A CONFIGURABLE LOW POWER HIGH FAN-IN MULTIPLEXER
    5.
    发明申请
    METHOD AND APPARATUS FOR A CONFIGURABLE LOW POWER HIGH FAN-IN MULTIPLEXER 有权
    一种可配置低功率高风扇多路复用器的方法和装置

    公开(公告)号：US20080303553A1

    公开(公告)日：2008-12-11

    申请号：US11759426

    申请日：2007-06-07

    申请人： OWEN CHIANG ,  Christopher M. Durham ,  Peter J. Klim ,  James D. Warnock

    发明人： OWEN CHIANG ,  Christopher M. Durham ,  Peter J. Klim ,  James D. Warnock

    IPC分类号： H03K19/20

    CPC分类号： H03K19/0008 ,  H03K17/005

    摘要： A configurable, low power high fan-in multiplexer (MUX) is disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.

    摘要翻译： 公开了一种可配置的低功率高风扇多路复用器（MUX）。 MUX电路包括多个电流控制元件，每个电流控制元件包括耦合到传输门的多个反相器。 每个电流控制元件接收对应于数据信号的数据信号和选择信号。 如果选择信号超过阈值（例如，逻辑“1”），则选择信号去激活上拉晶体管（例如，p型场效应晶体管），并且传输门使得相应的数据信号能够提供 输入到与MUX的输出耦合的逻辑门（例如，NAND门）。 如果选择信号不超过阈值，则选择信号激活上拉晶体管，并且传输门禁止相应的数据信号向逻辑门提供输入。

    Double-edge triggered scannable pulsed flip-flop for high frequency and/or low power applications
    6.
    发明申请
    Double-edge triggered scannable pulsed flip-flop for high frequency and/or low power applications 审中-公开
    用于高频和/或低功率应用的双边沿触发可扫描脉冲触发器

    公开(公告)号：US20080215941A1

    公开(公告)日：2008-09-04

    申请号：US12123107

    申请日：2008-05-19

    申请人： Christopher M. Durham ,  Jenny Fan ,  Peter J. Klim ,  Robert N. Krentler

    发明人： Christopher M. Durham ,  Jenny Fan ,  Peter J. Klim ,  Robert N. Krentler

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318541 ,  G01R31/318502 ,  G01R31/318575 ,  G01R31/318591

    摘要： A design structure embodied in a machine readable medium used in a design process, includes a circuit for data storage. The circuit includes a double edge clock generation circuit for generating a pulse clock signal having first and second clock pulses for each clock cycle of a system clock; a scan clock generation circuit for generating first and second scan clock signals; a scannable pulse flip-flop circuit having a data input and a data output that are connected with an internal storage node, the scannable pulse flip-flop circuit including a scan input and a scan output connected with the internal storage node, and receptive to the pulse clock signal and the scan clock signals. The scannable pulse flip-flop circuit is configured to be operable in a function mode of operation and a scan mode of operation.

    摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括用于数据存储的电路。 该电路包括一个双边沿时钟产生电路，用于产生具有用于系统时钟的每个时钟周期的第一和第二时钟脉冲的脉冲时钟信号; 扫描时钟产生电路，用于产生第一和第二扫描时钟信号; 具有与内部存储节点连接的数据输入和数据输出的可扫描脉冲触发器电路，所述可扫描脉冲触发器电路包括与内部存储节点连接的扫描输入和扫描输出，并且可接受 脉冲时钟信号和扫描时钟信号。 可扫描脉冲触发器电路被配置为在操作的功能模式和扫描操作模式下可操作。

    VIRTUAL POWER RAILS FOR INTEGRATED CIRCUITS
    7.
    发明申请
    VIRTUAL POWER RAILS FOR INTEGRATED CIRCUITS 有权
    用于集成电路的虚拟功率轨

    公开(公告)号：US20080123458A1

    公开(公告)日：2008-05-29

    申请号：US11458616

    申请日：2006-07-19

    申请人： Zhibin Cheng ,  Satyajit Dutta ,  Peter J. Klim

    发明人： Zhibin Cheng ,  Satyajit Dutta ,  Peter J. Klim

    IPC分类号： G11C5/14 ,  G05F3/02

    CPC分类号： G11C5/063 ,  G11C11/413

    摘要： Methods and apparatuses to decrease power consumption and reduce leakage current of integrated circuits are disclosed. New leakage power saving techniques for various types of integrated circuits, including cache memory circuits, are discussed. Embodiments comprise methods and apparatuses to reduce power consumption in integrated circuits by using virtual voltage rails, or virtual power rails, to supply power to integrated circuit loads. The methods and apparatuses generally involve using one or two virtual power control devices to “head” and “foot”, or sandwich, the integrated circuit loads from firm power supply rails. In these method embodiments, one or more elements sense the voltage of the virtual power rails, or nodes, and make adjustments to control the voltage at certain “virtual” voltage potentials. While controlling the voltage in this manner, the virtual power control devices may serve to restrict unnecessary current flow through the integrated circuit loads.

    摘要翻译： 公开了降低功耗并降低集成电路泄漏电流的方法和装置。 讨论了用于各种类型的集成电路（包括高速缓存存储器电路）的新的漏电省电技术。 实施例包括通过使用虚拟电压轨或虚拟电源轨来降低集成电路的功率消耗的方法和装置，以向集成电路负载供电。 所述方法和装置通常涉及使用一个或两个虚拟功率控制装置从牢固的电源轨道“集成”和“脚”或夹入集成电路负载。 在这些方法实施例中，一个或多个元件感测虚拟电源轨或节点的电压，并进行调整以控制某些“虚拟”电压电位下的电压。 在以这种方式控制电压的同时，虚拟功率控制装置可用于限制通过集成电路负载的不必要的电流。

    Electronic switch for decoupling capacitor
    8.
    发明授权
    Electronic switch for decoupling capacitor 失效
    用于去耦电容的电子开关

    公开(公告)号：US5506457A

    公开(公告)日：1996-04-09

    申请号：US418971

    申请日：1995-04-07

    申请人： Byron L. Krauter ,  Peter J. Klim ,  Tak H. Ning ,  Stanley E. Schuster ,  Lloyd A. Walls

    发明人： Byron L. Krauter ,  Peter J. Klim ,  Tak H. Ning ,  Stanley E. Schuster ,  Lloyd A. Walls

    IPC分类号： H01L27/08 ,  H03K17/22 ,  H01H83/20

    CPC分类号： H01L27/0805 ,  H03K17/22 ,  Y10T307/852

    摘要： An electronic switch circuit switches out bad decoupling capacitors on a high speed integrated circuit chip. The circuit comprises a control device that operates in the subthreshold or off device state to detect leakage in a decoupling capacitor. This control device operates in a low impedance state if the capacitor is good and in a high impedance sate if the capacitor is bad. A feedback circuit is connected from an internal node of the capacitor to a gate of the control device so that once a state of the capacitor is detected it can be stored on the gate of the control device. A single external signal source shared by a group of capacitors activates the control device to detect leakage in the capacitor. The circuit operates to switch out capacitors that fail during normal operation.

    摘要翻译： 电子开关电路在高速集成电路芯片上切断不良去耦电容。 该电路包括一个在亚阈值或者关断器件状态下操作以检测去耦电容器中的泄漏的控制装置。 如果电容器良好，则该控制装置工作在低阻抗状态，如果电容器坏，则其工作在高阻抗状态。 反馈电路从电容器的内部节点连接到控制装置的栅极，使得一旦电容器的状态被检测到，就可将其存储在控制装置的栅极上。 由一组电容器共享的单个外部信号源激活控制装置以检测电容器中的泄漏。 该电路用于切换在正常操作期间失败的电容器。

    Programable interrupt controller
    9.
    发明授权
    Programable interrupt controller 失效
    可编程中断控制器

    公开(公告)号：US5261107A

    公开(公告)日：1993-11-09

    申请号：US825336

    申请日：1992-01-23

    申请人： Peter J. Klim ,  Avery M. Lyford ,  Dennis L. Moeller

    发明人： Peter J. Klim ,  Avery M. Lyford ,  Dennis L. Moeller

    IPC分类号： G06F13/24 ,  G06F13/26 ,  G06F9/46

    CPC分类号： G06F13/26 ,  G06F13/24

    摘要： A programmable interrupt controller having a plurality of interrupt request inquest inputs and an interrupt request output for connection to a central processing unit (CPU) includes means for interrupting the CPU over the interrupt request output responsive to an interrupt request from any one of the interrupt request inputs and a priority resolver for assigning a priority position to each of the interrupt request inputs to create an interrupt priority hierarchy. The interrupt controller is programmable such that each interrupt request input may be independently established as responsive to either edge-triggered or level-triggered interrupt requests on a per interrupt basis. An initialization command word register of the interrupt controller has a bit corresponding to each of the interrupt request inputs. Programming each of the bits of the register to one of two states determines whether corresponding interrupt request inputs are edge-sensitive or level-sensitive.

    摘要翻译： 具有多个中断请求查询输入的可编程中断控制器和用于连接到中央处理单元（CPU）的中断请求输出包括响应于来自任一中断请求的中断请求而中断CPU的中断请求输出的装置 输入和优先级分解器，用于将优先级位置分配给每个中断请求输入以创建中断优先级层次。 中断控制器是可编程的，使得每个中断请求输入可以独立地建立为响应于每个中断的边沿触发或电平触发中断请求。 中断控制器的初始化命令字寄存器具有与每个中断请求输入相对应的位。 将寄存器的每个位编程为两种状态之一决定了相应的中断请求输入是边沿敏感还是对电平敏感。