公开(公告)号：US20110292728A1

公开(公告)日：2011-12-01

申请号：US13209241

申请日：2011-08-12

申请人： Hsin-Yi Ho ,  Ji-Yu Hung

发明人： Hsin-Yi Ho ,  Ji-Yu Hung

IPC分类号： G11C16/10 ,  G11C16/26

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  G11C16/3418 ,  G11C16/3427

摘要： A reading method for a multi-level cell (MLC) memory includes the following steps. A number of word line voltages are sequentially provided to an MLC memory cell. A number of bit line voltages corresponding to the word line voltages are sequentially provided to the MLC memory cell. One of the word line voltages is higher than another one of the word line voltages, and one of the bit line voltages corresponding to the one of the word line voltages is lower than another one of the bit line voltages corresponding to the another one of the word line voltages.

摘要翻译： 多级单元（MLC）存储器的读取方法包括以下步骤。 多个字线电压被顺序提供给MLC存储单元。 对应于字线电压的多个位线电压被依次提供给MLC存储单元。 字线电压之一高于另一个字线电压，并且与字线电压中的一个相对应的位线电压之一低于对应于另一个字线电压的另一个位线电压 字线电压。

公开(公告)号：US07804729B2

公开(公告)日：2010-09-28

申请号：US12271022

申请日：2008-11-14

申请人： Wen-Chiao Ho ,  Ji-Yu Hung ,  Chun-Hsiung Hung ,  Shuo-Nan Hung

发明人： Wen-Chiao Ho ,  Ji-Yu Hung ,  Chun-Hsiung Hung ,  Shuo-Nan Hung

IPC分类号： G11C7/04

CPC分类号： G11C7/08 ,  G11C7/04

摘要： A temperature compensation circuit includes a voltage generator, a comparator and an emulation cell array. The voltage generator provides a predetermined voltage and a reference voltage. The comparator has a first terminal for receiving the predetermined voltage, and a second terminal for receiving the reference voltage. The emulation cell array is coupled to the first terminal of the comparator. When a voltage of the first terminal of the comparator is discharged, via the emulation cell array, to be lower than the reference voltage, the comparator outputs a read timing control signal to control a sense amplifier to perform a sensing operation.

摘要翻译： 温度补偿电路包括电压发生器，比较器和仿真单元阵列。 电压发生器提供预定电压和参考电压。 比较器具有用于接收预定电压的第一端子和用于接收参考电压的第二端子。 仿真单元阵列耦合到比较器的第一端。 当比较器的第一端子的电压经由仿真单元阵列放电到低于参考电压时，比较器输出读取定时控制信号以控制读出放大器执行感测操作。

公开(公告)号：US08194462B2

公开(公告)日：2012-06-05

申请号：US13209241

申请日：2011-08-12

申请人： Hsin-Yi Ho ,  Ji-Yu Hung

发明人： Hsin-Yi Ho ,  Ji-Yu Hung

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  G11C16/3418 ,  G11C16/3427

摘要： A reading method for a multi-level cell (MLC) memory includes the following steps. A number of word line voltages are sequentially provided to an MLC memory cell. A number of bit line voltages corresponding to the word line voltages are sequentially provided to the MLC memory cell. One of the word line voltages is higher than another one of the word line voltages, and one of the bit line voltages corresponding to the one of the word line voltages is lower than another one of the bit line voltages corresponding to the another one of the word line voltages.

摘要翻译： 多级单元（MLC）存储器的读取方法包括以下步骤。 多个字线电压依次提供给MLC存储单元。 对应于字线电压的多个位线电压被依次提供给MLC存储单元。 字线电压之一高于另一个字线电压，并且与字线电压中的一个相对应的位线电压之一低于对应于另一个字线电压的另一个位线电压 字线电压。

公开(公告)号：US08724390B2

公开(公告)日：2014-05-13

申请号：US13245587

申请日：2011-09-26

申请人： Chun-Hsiung Hung ,  Shuo-Nan Hung ,  Ji-Yu Hung ,  Shih-Lin Huang ,  Fu-Tsang Wang

发明人： Chun-Hsiung Hung ,  Shuo-Nan Hung ,  Ji-Yu Hung ,  Shih-Lin Huang ,  Fu-Tsang Wang

IPC分类号： G11C11/34

CPC分类号： G11C16/24 ,  G11C16/0483 ,  G11C16/26 ,  G11C2216/14 ,  H01L27/1157 ,  H01L27/11578

摘要： Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for minimizing capacitance differences among the global bit lines.

摘要翻译： 这里描述了用于通过对选定的位线应用不同的偏置条件来补偿阵列中的存储器单元之间的阈值电压变化的技术。 本文还描述了将全局位线连接到3D阵列中的各种级别的存储器单元的技术，以提供最小化全局位线之间的电容差。

公开(公告)号：US20130141977A1

公开(公告)日：2013-06-06

申请号：US13310315

申请日：2011-12-02

申请人： Ji-Yu Hung

发明人： Ji-Yu Hung

IPC分类号： G11C16/26

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3418

摘要： A page buffer circuit is coupled to a bit line of a memory array. The page buffer circuit includes a latch storing different data during different phases of a multi-phase program operation. A preparation phase is after the program phase and after the program verify phase of the present multi-phase program operation. For the preparation phase, the control circuitry causes the latch to store the preparation data indicating whether to program the memory cell in a subsequent multi-phase program operation following the present multi-phase program operation. Results of the program verify phase, and contents of the latch at a start of the present multi-phase program operation, are sufficient to determine the preparation data.

摘要翻译： 页缓冲电路耦合到存储器阵列的位线。 页面缓冲电路包括在多阶段程序操作的不同阶段存储不同数据的锁存器。 准备阶段是在程序阶段之后和程序验证阶段之后的当前多阶段程序操作。 对于准备阶段，控制电路使锁存器存储指示在本多阶段程序操作之后的随后的多相程序操作中是否对存储单元进行编程的准备数据。 程序验证阶段的结果以及当前多阶段程序操作开始时的锁存器的内容足以确定准备数据。

公开(公告)号：US20100302863A1

公开(公告)日：2010-12-02

申请号：US12855799

申请日：2010-08-13

申请人： Hsin-Yi Ho ,  Ji-Yu Hung

发明人： Hsin-Yi Ho ,  Ji-Yu Hung

IPC分类号： G11C16/06

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  G11C16/3418 ,  G11C16/3427

摘要： A reading method for a multi-level cell (MLC) memory includes the following steps. A number of word line voltages are sequentially provided to an MLC memory cell. A number of bit line voltages corresponding to the word line voltages are sequentially provided to the MLC memory cell. One of the word line voltages is higher than another one of the word line voltages, and one of the bit line voltages corresponding to the one of the word line voltages is lower than another one of the bit line voltages corresponding to the another one of the word line voltages.

摘要翻译： 多级单元（MLC）存储器的读取方法包括以下步骤。 多个字线电压被顺序提供给MLC存储单元。 对应于字线电压的多个位线电压被依次提供给MLC存储单元。 字线电压之一高于另一个字线电压，并且与字线电压中的一个相对应的位线电压之一低于对应于另一个字线电压的另一个位线电压 字线电压。

公开(公告)号：US07796436B2

公开(公告)日：2010-09-14

申请号：US12167265

申请日：2008-07-03

申请人： Hsin-Yi Ho ,  Ji-Yu Hung

发明人： Hsin-Yi Ho ,  Ji-Yu Hung

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  G11C16/3418 ,  G11C16/3427

摘要： A reading method for a multi-level cell (MLC) memory includes the following steps. A number of word line voltages are sequentially provided to an MLC memory cell. A number of bit line voltages corresponding to the word line voltages are sequentially provided to the MLC memory cell. One of the word line voltages is higher than another one of the word line voltages, and one of the bit line voltages corresponding to the one of the word line voltages is lower than another one of the bit line voltages corresponding to the another one of the word line voltages.

摘要翻译： 多级单元（MLC）存储器的读取方法包括以下步骤。 多个字线电压被顺序提供给MLC存储单元。 对应于字线电压的多个位线电压依次提供给MLC存储单元。 字线电压之一高于另一个字线电压，并且与字线电压中的一个相对应的位线电压之一低于对应于另一个字线电压的另一个位线电压 字线电压。

公开(公告)号：US08792285B2

公开(公告)日：2014-07-29

申请号：US13310315

申请日：2011-12-02

申请人： Ji-Yu Hung

发明人： Ji-Yu Hung

IPC分类号： G11C7/10

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3418

摘要： A page buffer circuit is coupled to a bit line of a memory array. The page buffer circuit includes a latch storing different data during different phases of a multi-phase program operation. A preparation phase is after the program phase and after the program verify phase of the present multi-phase program operation. For the preparation phase, the control circuitry causes the latch to store the preparation data indicating whether to program the memory cell in a subsequent multi-phase program operation following the present multi-phase program operation. Results of the program verify phase, and contents of the latch at a start of the present multi-phase program operation, are sufficient to determine the preparation data.

摘要翻译： 页缓冲电路耦合到存储器阵列的位线。 页面缓冲电路包括在多阶段程序操作的不同阶段存储不同数据的锁存器。 准备阶段是在程序阶段之后和程序验证阶段之后的当前多阶段程序操作。 对于准备阶段，控制电路使锁存器存储指示在本多阶段程序操作之后的随后的多相程序操作中是否对存储单元进行编程的准备数据。 程序验证阶段的结果以及当前多阶段程序操作开始时的锁存器的内容足以确定准备数据。

公开(公告)号：US20120182804A1

公开(公告)日：2012-07-19

申请号：US13245587

申请日：2011-09-26

申请人： CHUN-HSIUNG HUNG ,  Shuo-Nan Hung ,  Ji-Yu Hung ,  Shih-Lin Huang ,  Fu-Tsang Wang

发明人： CHUN-HSIUNG HUNG ,  Shuo-Nan Hung ,  Ji-Yu Hung ,  Shih-Lin Huang ,  Fu-Tsang Wang

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/24 ,  G11C16/0483 ,  G11C16/26 ,  G11C2216/14 ,  H01L27/1157 ,  H01L27/11578

摘要： Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for minimizing capacitance differences among the global bit lines.

摘要翻译： 这里描述了用于通过对选定的位线应用不同的偏置条件来补偿阵列中的存储器单元之间的阈值电压变化的技术。 本文还描述了将全局位线连接到3D阵列中的各种级别的存储器单元的技术，以提供最小化全局位线之间的电容差。

公开(公告)号：US08208332B2

公开(公告)日：2012-06-26

申请号：US12870313

申请日：2010-08-27

申请人： Wen-Chiao Ho ,  Ji-Yu Hung ,  Chun-Hsiung Hung ,  Shuo-Nan Hung

发明人： Wen-Chiao Ho ,  Ji-Yu Hung ,  Chun-Hsiung Hung ,  Shuo-Nan Hung

IPC分类号： G11C7/04

CPC分类号： G11C7/08 ,  G11C7/04

摘要： A compensation circuit includes a comparator and an emulation circuit. The comparator has a first terminal, and a second terminal for receiving a reference voltage. The emulation circuit is coupled to the first terminal of the comparator. The emulation circuit responses to the temperature, so that the comparator outputs a read timing control signal at a first time spot, or outputs the read timing control signal at a second time spot, the first time spot is later than the second time spot.

摘要翻译： 补偿电路包括比较器和仿真电路。 比较器具有第一端子和用于接收参考电压的第二端子。 仿真电路耦合到比较器的第一端。 仿真电路响应于温度，使得比较器在第一时间点输出读定时控制信号，或者在第二时间点输出读定时控制信号，第一时间点晚于第二时间点。