公开(公告)号：US20130128191A1

公开(公告)日：2013-05-23

申请号：US13380228

申请日：2011-11-25

Applicant: Jehao Hsu ,  Xiaohui Yao ,  Jing-feng Xue ,  Chengcai Dong

Inventor： Jehao Hsu ,  Xiaohui Yao ,  Jing-feng Xue ,  Chengcai Dong

IPC: G02F1/1335

CPC classification number: G02F1/13363

Abstract: The present invention provides a display pane comprising a liquid crystal cell and two polarizers disposed at both sides of the liquid crystal cell, wherein one of the polarizers at one side of the liquid crystal cell includes a compensation film, and a first optical path difference R0 of the compensation film is 0.15 to 0.35 times an optical path difference R of the liquid crystal cell. The liquid crystal display pane of the present invention can have a low cost and a wide viewing angle, so as to solve the problems that the contrast of the conventional display panel is reduced, and the dual compensation films have a higher cost.

Abstract translation: 本发明提供了一种显示面板，包括液晶单元和设置在液晶单元两侧的两个偏振器，其中液晶单元一侧的偏振器之一包括补偿膜，第一光程差R0 的补偿膜的液晶单元的光程差R的0.15〜0.35倍。 本发明的液晶显示面板可以具有低成本和宽的视角，从而解决了传统显示面板的对比度降低的问题，并且双补偿膜具有较高的成本。

公开(公告)号：US20130126467A1

公开(公告)日：2013-05-23

申请号：US13379852

申请日：2011-11-24

Applicant: Jing-feng Xue ,  Jehao Hsu

Inventor： Jing-feng Xue ,  Jehao Hsu

IPC: H01B13/00

CPC classification number: H01L21/0273 ,  H01L21/32139 ,  H01L27/124 ,  H01L27/1288

Abstract: The present invention discloses a method for manufacturing conductive lines with small line-to-line space. The method for manufacturing conductive lines is to coat photoresist on a conductor layer firstly, after exposure and development treatments, then further perform an ashing treatment to completely remove the corresponding part of the photoresist that is corresponding to the exposure area, and then perform an etching step for the conductor layer to form the required conductive lines. The method provided by the present invention can manufacture wire patterns that meet the requirement of small line-to-line space under a condition that the exposure apparatus has limited exposure accuracy.

Abstract translation: 本发明公开了一种具有小线间距的导线的制造方法。 制造导线的方法是首先在导体层上涂覆光致抗蚀剂，在曝光和显影处理之后，进一步进行灰化处理以完全除去对应于曝光区域的光致抗蚀剂的相应部分，然后进行蚀刻 导体层形成所需导电线的步骤。 本发明提供的方法可以在曝光装置具有有限的曝光精度的条件下制造满足小线对空间要求的线图案。

公开(公告)号：US08329518B1

公开(公告)日：2012-12-11

申请号：US13376636

申请日：2011-10-11

Applicant: Jing-feng Xue ,  Jehao Hsu ,  Xiaohui Yao

Inventor： Jing-feng Xue ,  Jehao Hsu ,  Xiaohui Yao

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/469

CPC classification number: H01L29/66765 ,  H01L21/32139 ,  H01L27/1288

Abstract: The present invention provides methods for manufacturing a thin film transistor (TFT) array substrate and a display panel. The method for manufacturing the TFT array substrate comprises the following steps: forming a plurality of gate electrodes, a gate insulating layer, a semiconductor layer, an ohmic contact layer, an electrode layer and a first photo-resist layer on a transparent substrate in sequence; patterning the first photo-resist layer; etching the ohmic contact layer and the electrode layer; coating a second photo-resist layer on the patterned first photo-resist layer and in the channels; removing the second photo-resist layer on the patterned first photo-resist layer and to allow the second photo-resist layer in the channels to remain therein; etching the semiconductor layer; removing the patterned first photo-resist layer and the second photo-resist layer; forming a passivation layer on the channels, the source electrodes and the drain electrodes; and forming a pixel electrode layer on the passivation layer. The present invention can reduce an amount of the required masks in the fabrication process, and only one wet etching is required to etch the metal material on the TFT array substrate.

Abstract translation: 本发明提供了制造薄膜晶体管（TFT）阵列基板和显示面板的方法。 制造TFT阵列基板的方法包括以下步骤：依次在透明基板上形成多个栅电极，栅极绝缘层，半导体层，欧姆接触层，电极层和第一光致抗蚀剂层 ; 图案化第一光致抗蚀剂层; 蚀刻欧姆接触层和电极层; 在图案化的第一光致抗蚀剂层和通道中涂覆第二光致抗蚀剂层; 去除图案化的第一光致抗蚀剂层上的第二光致抗蚀剂层并允许通道中的第二光致抗蚀剂层保留在其中; 蚀刻半导体层; 去除图案化的第一光致抗蚀剂层和第二光致抗蚀剂层; 在沟道，源电极和漏电极上形成钝化层; 以及在所述钝化层上形成像素电极层。 本发明可以减少制造工艺中所需的掩模的量，并且仅需要一次湿式蚀刻来蚀刻TFT阵列基板上的金属材料。

公开(公告)号：US09122102B2

公开(公告)日：2015-09-01

申请号：US13512577

申请日：2012-03-13

Applicant: Xiaohui Yao ,  Jehao Hsu ,  Jing-feng Xue ,  Chengcai Dong

Inventor： Xiaohui Yao ,  Jehao Hsu ,  Jing-feng Xue ,  Chengcai Dong

IPC: G02F1/1337 ,  G02F1/1343

CPC classification number: G02F1/133707 ,  G02F1/134336 ,  G02F2001/133761 ,  G02F2001/134318

Abstract: A patterned vertical alignment (PVA) pixel electrode is disclosed. The PVA pixel electrode includes a first electrode and a second electrode. The first and second electrodes form a pre-tilt angle with respect to a periphery of the pixel. By disposing unequal lengths of indium-tin oxide (ITO) gaps at a periphery of the first and second electrodes, a distance between the first and second electrodes gradually becomes shortened from the center of the pixel outwards. The ITO gaps which are disposed at the periphery of a thin film transistor (TFT)-array substrate and/or a color filter (CF) are adjusted for eliminating a fringe field effect in the present invention, which a transmittance on the pixel regions is improved and an effect of image display quality is enhanced.

Abstract translation: 公开了图案化垂直取向（PVA）像素电极。 PVA像素电极包括第一电极和第二电极。 第一和第二电极相对于像素的周边形成预倾角。 通过在第一和第二电极的周围设置不等长的铟锡氧化物（ITO）间隙，第一和第二电极之间的距离从像素的中心向外逐渐变短。 调整设置在薄膜晶体管（TFT） - 射线基板和/或滤色器（CF）的周围的ITO间隙，以消除本发明中的边缘场效应，像素区域上的透射率为 改进了图像显示质量的效果。

公开(公告)号：US20130235317A1

公开(公告)日：2013-09-12

申请号：US13512577

申请日：2012-03-13

Applicant: Xiaohui Yao ,  Jehao Hsu ,  Jing-feng Xue ,  Chengcai Dong

Inventor： Xiaohui Yao ,  Jehao Hsu ,  Jing-feng Xue ,  Chengcai Dong

IPC: G02F1/1343

CPC classification number: G02F1/133707 ,  G02F1/134336 ,  G02F2001/133761 ,  G02F2001/134318

Abstract: A patterned vertical alignment (PVA) pixel electrode is disclosed. The PVA pixel electrode includes a first electrode and a second electrode. The first and second electrodes form a pre-tilt angle with respect to a periphery of the pixel. By disposing unequal lengths of indium-tin oxide (ITO) gaps at a periphery of the first and second electrodes, a distance between the first and second electrodes gradually becomes shortened from the center of the pixel outwards. The ITO gaps which are disposed at the periphery of a thin film transistor (TFT)-array substrate and/or a color filter (CF) are adjusted for eliminating a fringe field effect in the present invention, which a transmittance on the pixel regions is improved and an effect of image display quality is enhanced.

Abstract translation: 公开了图案化垂直取向（PVA）像素电极。 PVA像素电极包括第一电极和第二电极。 第一和第二电极相对于像素的周边形成预倾角。 通过在第一和第二电极的周围设置不等长的铟锡氧化物（ITO）间隙，第一和第二电极之间的距离从像素的中心向外逐渐变短。 调整设置在薄膜晶体管（TFT） - 射线基板和/或滤色器（CF）的周围的ITO间隙，以消除本发明中的边缘场效应，像素区域上的透射率为 改进了图像显示质量的效果。