利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

4 条记录 (耗时 0.014 秒)

    Determining feasibility of IC edits
    1.
    发明申请
    Determining feasibility of IC edits 有权
    确定IC编辑的可行性

    公开(公告)号：US20050273745A1

    公开(公告)日：2005-12-08

    申请号：US10861294

    申请日：2004-06-04

    申请人： John Bach ,  Rand Carawan ,  Hemant Joshi ,  David Thomas

    发明人： John Bach ,  Rand Carawan ,  Hemant Joshi ,  David Thomas

    IPC分类号： G06F9/45 ,  G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5081

    摘要： A computer method of analyzing an integrated circuit (“IC”) masked design data, comprising grouping into a cluster areas of layers preceding a target metal layer that are suitable for milling, deleting portions of the target metal layer that do not meet minimum tool spacing requirements to produce a modified metal layer, deleting portions of the modified metal layer that do not meet minimum design rule width requirements to produce a final metal layer, and comparing the final metal layer and the cluster to identify common areas.

    摘要翻译： 一种分析集成电路（“IC”）掩蔽设计数据的计算机方法，包括将适合于铣削的目标金属层之前的层分组成组合，删除目标金属层的不符合最小刀具间距的部分 要求生产改性金属层，删除不符合最小设计规则宽度要求的部分修饰金属层以产生最终金属层，以及比较最终金属层和簇以识别公共区域。

    Method of cross-mapping integrated circuit design formats
    4.
    发明授权
    Method of cross-mapping integrated circuit design formats 有权
    交叉映射集成电路设计格式的方法

    公开(公告)号：US06941530B2

    公开(公告)日：2005-09-06

    申请号：US10395476

    申请日：2003-03-24

    申请人： Hemant Joshi ,  David A. Thomas ,  John Bach ,  Rand B. Carawan

    发明人： Hemant Joshi ,  David A. Thomas ,  John Bach ,  Rand B. Carawan

    IPC分类号： G01R31/317 ,  G06F17/50

    CPC分类号： G01R31/31707 ,  G01R31/31718 ,  G06F17/5081

    摘要： A method of cross-mapping integrated circuit (“IC”) elements nets in a IC and/or directing a probe to points on an IC to achieve minimal interference from adjacent structures is disclosed. The method of provides a more streamlined approach than referencing points from a physical layout representation of the IC to the actual IC being tested. The improved correlation between the actual packaged IC and the layout of the IC is accomplished using artificial locator cells. Preferably, the artificial locator cells are generated from mathematical operations of the extracted version of the layout, and they further provide coordinate information for where minimal interference from adjacent structures may be accomplished. Artificial locator cells may be generated from a layout representing a hierarchical representation or alternately each element that is instantiated from a reference library may already have artificial locator cells included.

    摘要翻译： 公开了一种将集成电路（“IC”）元件网络交叉映射到IC中和/或将探针引导到IC上的点以实现来自相邻结构的最小干扰的方法。 该方法提供了一种比从IC的物理布局表示到正在测试的实际IC的点的更简化的方法。 实际封装IC和IC布局之间的改善相关性是使用人工定位器单元完成的。 优选地，人造定位器单元是从所提取的布局版本的数学运算产生的，并且它们还提供了可以实现来自相邻结构的最小干扰的坐标信息。 可以从表示层次表示的布局生成人工定位单元，或者替代地，从参考库中实例化的每个元素可能已经包括人造定位单元。