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21 条记录 (耗时 0.042 秒)

    Determining feasibility of IC edits
    1.
    发明申请
    Determining feasibility of IC edits 有权
    确定IC编辑的可行性

    公开(公告)号：US20050273745A1

    公开(公告)日：2005-12-08

    申请号：US10861294

    申请日：2004-06-04

    申请人： John Bach ,  Rand Carawan ,  Hemant Joshi ,  David Thomas

    发明人： John Bach ,  Rand Carawan ,  Hemant Joshi ,  David Thomas

    IPC分类号： G06F9/45 ,  G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5081

    摘要： A computer method of analyzing an integrated circuit (“IC”) masked design data, comprising grouping into a cluster areas of layers preceding a target metal layer that are suitable for milling, deleting portions of the target metal layer that do not meet minimum tool spacing requirements to produce a modified metal layer, deleting portions of the modified metal layer that do not meet minimum design rule width requirements to produce a final metal layer, and comparing the final metal layer and the cluster to identify common areas.

    摘要翻译： 一种分析集成电路（“IC”）掩蔽设计数据的计算机方法，包括将适合于铣削的目标金属层之前的层分组成组合，删除目标金属层的不符合最小刀具间距的部分 要求生产改性金属层，删除不符合最小设计规则宽度要求的部分修饰金属层以产生最终金属层，以及比较最终金属层和簇以识别公共区域。

    Method of cross-mapping integrated circuit design formats
    2.
    发明授权
    Method of cross-mapping integrated circuit design formats 有权
    交叉映射集成电路设计格式的方法

    公开(公告)号：US06941530B2

    公开(公告)日：2005-09-06

    申请号：US10395476

    申请日：2003-03-24

    申请人： Hemant Joshi ,  David A. Thomas ,  John Bach ,  Rand B. Carawan

    发明人： Hemant Joshi ,  David A. Thomas ,  John Bach ,  Rand B. Carawan

    IPC分类号： G01R31/317 ,  G06F17/50

    CPC分类号： G01R31/31707 ,  G01R31/31718 ,  G06F17/5081

    摘要： A method of cross-mapping integrated circuit (“IC”) elements nets in a IC and/or directing a probe to points on an IC to achieve minimal interference from adjacent structures is disclosed. The method of provides a more streamlined approach than referencing points from a physical layout representation of the IC to the actual IC being tested. The improved correlation between the actual packaged IC and the layout of the IC is accomplished using artificial locator cells. Preferably, the artificial locator cells are generated from mathematical operations of the extracted version of the layout, and they further provide coordinate information for where minimal interference from adjacent structures may be accomplished. Artificial locator cells may be generated from a layout representing a hierarchical representation or alternately each element that is instantiated from a reference library may already have artificial locator cells included.

    摘要翻译： 公开了一种将集成电路（“IC”）元件网络交叉映射到IC中和/或将探针引导到IC上的点以实现来自相邻结构的最小干扰的方法。 该方法提供了一种比从IC的物理布局表示到正在测试的实际IC的点的更简化的方法。 实际封装IC和IC布局之间的改善相关性是使用人工定位器单元完成的。 优选地，人造定位器单元是从所提取的布局版本的数学运算产生的，并且它们还提供了可以实现来自相邻结构的最小干扰的坐标信息。 可以从表示层次表示的布局生成人工定位单元，或者替代地，从参考库中实例化的每个元素可能已经包括人造定位单元。

    System and method for setup and hold characterization in integrated circuit cells
    8.
    发明授权
    System and method for setup and hold characterization in integrated circuit cells 有权
    用于在集成电路单元中建立和保持表征的系统和方法

    公开(公告)号：US06640330B1

    公开(公告)日：2003-10-28

    申请号：US09841797

    申请日：2001-04-24

    申请人： Hemant Joshi

    发明人： Hemant Joshi

    IPC分类号： G06E1750

    CPC分类号： G06F17/5022

    摘要： An invention is disclosed for setup and hold time characterization in an integrated circuit cell. A setup time is obtained for a first constraint pin. A setup time is also calculated for a test point defined in the integrated circuit cell using the setup time for the first constraint pin and a first propagation delay from the first constraint pin to the test point. A setup time for a second constraint pin is determined based on the setup time for the test point and a second propagation delay from the second constraint pin to the test point. In addition to the setup time, a hold time can be obtained for the first constraint pin, and a hold time for the test point can be calculated using the hold time for the first constraint pin and the first propagation delay. Further, a hold time for the second constraint pin can be determined based on the hold time for the test point and the second propagation delay.

    摘要翻译： 公开了用于集成电路单元中的建立和保持时间表征的发明。 获得第一个约束引脚的建立时间。 还使用第一约束引脚的建立时间和从第一约束引脚到测试点的第一传播延迟来计算在集成电路单元中定义的测试点的建立时间。 基于测试点的建立时间和从第二约束引脚到测试点的第二传播延迟来确定第二约束引脚的建立时间。 除了建立时间之外，可以获得第一约束引脚的保持时间，并且可以使用第一约束引脚的保持时间和第一传播延迟来计算测试点的保持时间。 此外，可以基于测试点的保持时间和第二传播延迟来确定第二约束引脚的保持时间。

    Compounds as diacylglycerol acyltransferase inhibitors
    9.
    发明授权
    Compounds as diacylglycerol acyltransferase inhibitors 有权
    化合物作为二酰基甘油酰基转移酶抑制剂

    公开(公告)号：US08859536B2

    公开(公告)日：2014-10-14

    申请号：US14118976

    申请日：2012-05-18

    申请人： Donghui Qin ,  Mui Cheung ,  Hemant Joshi ,  Raghuram Tangirala ,  Sridhar Reddy Bethi

    发明人： Donghui Qin ,  Mui Cheung ,  Hemant Joshi ,  Raghuram Tangirala ,  Sridhar Reddy Bethi

    IPC分类号： C07D498/04 ,  A61K31/519 ,  C07D519/00

    CPC分类号： C07D519/00 ,  C07D498/04

    摘要： This invention relates to novel compounds which are inhibitors of acyl coenzymeA: diacylglycerol acyltransferase 1 (DGAT-1), to pharmaceutical compositions containing them, to processes for their preparation, and to their use in therapy for the prevention or treatment of diseases related to DGAT-1 dysfunction or where modulation of DGAT-1 activity may have therapeutic benefit including but not limited to obesity, obesity related disorders, hypertriglyceridemia, hyperlipoproteinemia, chylomicronemia, dyslipidemia, non-alcoholic steatohepatitis, diabetes, insulin resistance, metabolic syndrome, hepatitis C virus infection and acne or other skin disorders.

    摘要翻译： 本发明涉及作为酰基辅酶A：二酰基甘油酰基转移酶1（DGAT-1）的抑制剂的新化合物，含有它们的药物组合物，其制备方法及其在治疗中用于预防或治疗与DGAT有关的疾病 -1功能障碍或DGAT-1活性的调节可能具有治疗益处，包括但不限于肥胖症，肥胖相关疾病，高甘油三酯血症，高脂蛋白血症，乳糜微粒血症，血脂异常，非酒精性脂肪性肝炎，糖尿病，胰岛素抵抗，代谢综合征，丙型肝炎病毒 感染和痤疮或其他皮肤疾病。