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19 条记录 (耗时 0.015 秒)

    HIGH PERFORMANCE PROBABILISTIC RATE POLICER
    1.
    发明申请
    HIGH PERFORMANCE PROBABILISTIC RATE POLICER 有权
    高性能概率速率策略器

    公开(公告)号：US20100177638A1

    公开(公告)日：2010-07-15

    申请号：US12732370

    申请日：2010-03-26

    申请人： Dennis C. Ferguson ,  Devereaux C. Chen ,  John W. Stewart, III ,  James Washburn ,  Jeffrey R. Zimmer

    发明人： Dennis C. Ferguson ,  Devereaux C. Chen ,  John W. Stewart, III ,  James Washburn ,  Jeffrey R. Zimmer

    IPC分类号： H04L12/56

    CPC分类号： H04L47/10 ,  H04L47/20 ,  H04L47/39

    摘要： A data flow rate policer enforces data flow policies for a number of data flows using a probabilistic policy enforcement mechanism. The policer includes a memory that stores the state of each data flow in a compact data structure. Additionally, the policer includes one or more policing engines that implement the actual data flow policies based on information derived from the data structures. The policing engines may be implemented in hardware to increase performance.

    摘要翻译： 数据流速策略器使用概率策略执行机制来执行多个数据流的数据流策略。 监管者包括一个存储器，它将每个数据流的状态存储在紧凑的数据结构中。 另外，监管者还包括一个或多个监管引擎，其基于从数据结构导出的信息来实现实际的数据流策略。 警务引擎可以以硬件实现以提高性能。

    Bus executed scan testing method and apparatus
    2.
    发明授权
    Bus executed scan testing method and apparatus 失效
    总线执行扫描测试方法和设备

    公开(公告)号：US4947395A

    公开(公告)日：1990-08-07

    申请号：US308917

    申请日：1989-02-10

    申请人： Philip W. Bullinger ,  Thomas L. Langford, II ,  John W. Stewart

    发明人： Philip W. Bullinger ,  Thomas L. Langford, II ,  John W. Stewart

    IPC分类号： G06F11/22 ,  G01R31/3185 ,  G06F11/27

    CPC分类号： G01R31/318558 ,  G06F11/27

    摘要： For LSI/VLSI integrated circuits which inherently have an address decoder and a data bus, a scan testing method and apparatus is presented which does not require additional pin connections to be dedicated for scan test implementation. Counter to the Joint Test Action Group approach, the present invention uses additional registers, multiplexers, and decoders in conjunction with the existing buses to provide test access to otherwise embedded layers of logic circuitry, without the addition of a single pin connection to a integrated circuit chip package. Further, since this test method and apparatus uses the data bus and registers just as the rest of the chip, slow and complex d.c. level shifting equipment is not required.

    Solenoid driver circuit
    3.
    发明授权
    Solenoid driver circuit 失效
    电磁线圈驱动电路

    公开(公告)号：US4059844A

    公开(公告)日：1977-11-22

    申请号：US693035

    申请日：1976-06-04

    申请人： John W. Stewart

    发明人： John W. Stewart

    IPC分类号： H01F7/18 ,  H01H47/32

    CPC分类号： H01H47/325

    摘要： A driver circuit for limiting the magnitude of current flowing through a solenoid wherein the level of the current flowing through the solenoid is sensed and fed back to a driving switch. A level of current above a set level cuts off the drive voltage allowing the current in the solenoid to decay. A timing means fixes the time that the driving switch is off. During off times a conserving voltage is applied to the solenoid to prevent the rapid decay of the solenoid current.

    摘要翻译： 一种用于限制流过螺线管的电流的大小的驱动器电路，其中流过螺线管的电流的电平被感测并反馈到驱动开关。 高于设定电平的电流电平会切断驱动电压，使电磁铁中的电流衰减。 定时意味着修复驱动开关关闭的时间。 在关闭时间期间，向螺线管施加节电电压以防止螺线管电流的快速衰减。

    Automatic establishment of network performance monitoring communities using routing protocols
    6.
    发明授权
    Automatic establishment of network performance monitoring communities using routing protocols 有权
    使用路由协议自动建立网络性能监控社区

    公开(公告)号：US07606887B1

    公开(公告)日：2009-10-20

    申请号：US10660303

    申请日：2003-09-11

    申请人： John W Stewart ,  Wendy R Cartee ,  Joe Truman

    发明人： John W Stewart ,  Wendy R Cartee ,  Joe Truman

    IPC分类号： G06F15/173

    CPC分类号： H04L43/0852 ,  H04L41/5003 ,  H04L41/5009 ,  H04L45/26 ,  H04L45/72

    摘要： Techniques are described for monitoring performance of a network. Particularly, network devices within the network exchange routing communications in accordance with one or more routing protocols, such as the Border Gateway Protocol (BGP), to automatically establish a community for monitoring performance throughout the network. Upon establishing the community, the network devices of the community exchange performance probes to collect comprehensive performance information for the network. This performance information may be aggregated via one or more computing devices. Using the aggregated performance information, numerous network performance characteristics may be computed, including delay, jitter, throughput, availability and packet loss.

    摘要翻译： 描述了用于监视网络性能的技术。 特别地，网络内的网络设备根据诸如边界网关协议（BGP）的一个或多个路由协议交换路由通信，以自动建立一个用于监控整个网络的性能的社区。 建立社区后，社区网络设备交换性能探测，收集网络综合性能信息。 可以经由一个或多个计算设备来聚合该性能信息。 使用聚合的性能信息，可以计算许多网络性能特征，包括延迟，抖动，吞吐量，可用性和分组丢失。

    Drive circuit
    7.
    发明授权
    Drive circuit 失效
    驱动电路

    公开(公告)号：US4071877A

    公开(公告)日：1978-01-31

    申请号：US627736

    申请日：1975-10-31

    申请人： John W. Stewart ,  Ronald L. Bruckner

    发明人： John W. Stewart ,  Ronald L. Bruckner

    IPC分类号： B41J9/44 ,  H01F7/18 ,  H01H47/32

    CPC分类号： H01F7/1877 ,  B41J9/44 ,  H01F7/1883

    摘要： A circuit provides means for driving a load under control of a plurality of signals including a drive timing signal which is given a maximum permissible duration by the circuit to prevent damage to the load, an operating signal, and an inhibit signal which prevents operation in case of excessively low power supply voltage. A power supply of opposite polarity is connected to the load so that the load rapidly dissipates its energy into said power supply at the time of turn-off of the drive circuit.

    摘要翻译： 电路提供用于在多个信号的控制下驱动负载的装置，包括通过电路给予最大允许持续时间的驱动定时信号，以防止对负载的损坏，操作信号和防止操作的禁止信号 电源电压过低。 相反极性的电源连接到负载，使得负载在驱动电路关断时将其能量快速耗散到所述电源中。

    Automatic establishment of network performance monitoring communities using routing protocols
    9.
    发明授权
    Automatic establishment of network performance monitoring communities using routing protocols 有权
    使用路由协议自动建立网络性能监控社区

    公开(公告)号：US07987257B1

    公开(公告)日：2011-07-26

    申请号：US12582634

    申请日：2009-10-20

    申请人： John W. Stewart ,  Wendy R. Cartee ,  Truman Joe

    发明人： John W. Stewart ,  Wendy R. Cartee ,  Truman Joe

    IPC分类号： G06F15/173

    CPC分类号： H04L43/0852 ,  H04L41/5003 ,  H04L41/5009 ,  H04L45/26 ,  H04L45/72

    摘要： Techniques are described for monitoring performance of a network. Particularly, network devices within the network exchange routing communications in accordance with one or more routing protocols, such as the Border Gateway Protocol (BGP), to automatically establish a community for monitoring performance throughout the network. Upon establishing the community, the network devices of the community exchange performance probes to collect comprehensive performance information for the network. This performance information may be aggregated via one or more computing devices. Using the aggregated performance information, numerous network performance characteristics may be computed, including delay, jitter, throughput, availability and packet loss.

    摘要翻译： 描述了用于监视网络性能的技术。 特别地，网络内的网络设备根据诸如边界网关协议（BGP）的一个或多个路由协议交换路由通信，以自动建立一个用于监控整个网络的性能的社区。 建立社区后，社区网络设备交换性能探测，收集网络综合性能信息。 可以经由一个或多个计算设备来聚合该性能信息。 使用聚合的性能信息，可以计算许多网络性能特征，包括延迟，抖动，吞吐量，可用性和分组丢失。

    Digitally controlled delay circuit
    10.
    发明授权
    Digitally controlled delay circuit 失效
    数字控制延时电路

    公开(公告)号：US5111085A

    公开(公告)日：1992-05-05

    申请号：US43778

    申请日：1987-04-29

    申请人： John W. Stewart

    发明人： John W. Stewart

    IPC分类号： H03K5/00 ,  H03K5/13

    CPC分类号： H03K5/131 ,  H03K5/133 ,  H03K2005/00065 ,  H03K2005/00195

    摘要： A first inverter circuit is coupled between a first voltage source and a reference potential by a plurality of cascaded transistors. Each of the cascaded transistors has a control gate which may be selected to bring the resistance of the transistor into circuit with the inverter circuit to control the charging rate of a distributed capacitance. An output circuit coupled to the first inverter circuit provides the distributed capacitance and an inverted buffered output. The output circuit also includes an output which may be connected to another circuit of the present invention to form a cascaded delay circuit and to receive a reset signal for resetting the cascaded delay circuit.

    摘要翻译： 第一反相器电路通过多个级联晶体管耦合在第一电压源和参考电位之间。 每个级联晶体管具有控制栅极，其可以被选择以使晶体管的电阻与逆变器电路进行电路以控制分布电容的充电速率。 耦合到第一反相器电路的输出电路提供分布电容和反相缓冲输出。 输出电路还包括可以连接到本发明的另一个电路的输出，以形成级联的延迟电路并且接收用于重置级联延迟电路的复位信号。