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公开(公告)号：US08091000B2
公开(公告)日：2012-01-03
申请号：US12540602
申请日：2009-08-13
CPC分类号： G11C29/52 , G06F11/1024 , G11C29/88 , G11C29/883 , G11C2029/0409
摘要： An apparatus and methods are disclosed herein for identifying and avoiding attempts to access a defective portion of memory. Errors associated with portions of memory, such as a cache memory, are tracked over time enabling detection of both hard and erratic errors. Based on the number of errors tracked over time for a portion of memory, it is determined if the portion of memory is defective. In response to determining portion of memory is defective, the portion of memory is disabled. The portion of memory may be flushed and moved before being disable. Additionally, disabling the portion of memory may be conditioned upon determining if it is allowable to disable the portion of memory.
摘要翻译： 本文公开了一种用于识别和避免访问存储器的缺陷部分的尝试的装置和方法。 与存储器部分相关联的错误（如高速缓冲存储器）随时间被跟踪，从而能够检测到错误和错误的错误。 基于存储器的一部分随时间跟踪的错误的数量，确定存储器的部分是否有缺陷。 响应于存储器的确定部分有缺陷，存储器的该部分被禁用。 存储器的一部分可能在禁用之前被刷新并移动。 此外，禁止部分存储器可以在确定是否允许禁用存储器部分的情况下进行调节。
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公开(公告)号：US20080010566A1
公开(公告)日：2008-01-10
申请号：US11472870
申请日：2006-06-21
IPC分类号： G11C29/00
CPC分类号： G11C29/52 , G06F11/1024 , G11C29/88 , G11C29/883 , G11C2029/0409
摘要： Systems and methods are disclosed herein for identifying and avoiding attempts to access a defective portion of memory. Various techniques are provided for detecting a defect in a portion of memory and dynamically avoiding future attempts to access the defective portion of memory. More specifically, the techniques detect and avoid both hard and erratic errors.
摘要翻译： 本文公开了用于识别和避免访问存储器的缺陷部分的尝试的系统和方法。 提供各种技术来检测存储器的一部分中的缺陷并且动态地避免将来尝试访问存储器的缺陷部分。 更具体地说，这些技术可以检测并避免错误和错误。
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公开(公告)号：US20100058109A1
公开(公告)日：2010-03-04
申请号：US12614535
申请日：2009-11-09
CPC分类号： G11C29/52 , G06F11/1024 , G11C29/88 , G11C29/883 , G11C2029/0409
摘要： An apparatus and methods are disclosed herein for identifying and avoiding attempts to access a defective portion of memory. Errors associated with portions of memory, such as a cache memory, are tracked over time enabling detection of both hard and erratic errors. Based on the number of errors tracked over time for a portion of memory, it is determined if the portion of memory is defective. In response to determining portion of memory is defective, the portion of memory is disabled. The portion of memory may be flushed and moved before being disable. Additionally, disabling the portion of memory may be conditioned upon determining if it is allowable to disable the portion of memory.
摘要翻译： 本文公开了一种用于识别和避免访问存储器的缺陷部分的尝试的装置和方法。 与存储器部分相关联的错误（如高速缓冲存储器）随时间被跟踪，从而能够检测到错误和错误的错误。 基于存储器的一部分随时间跟踪的错误的数量，确定存储器的部分是否有缺陷。 响应于存储器的确定部分有缺陷，存储器的该部分被禁用。 存储器的一部分可能在禁用之前被刷新并移动。 此外，禁止部分存储器可以在确定是否允许禁用存储器部分的情况下进行调节。
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公开(公告)号：US07657767B2
公开(公告)日：2010-02-02
申请号：US11174204
申请日：2005-06-30
申请人： Stefan Rusu , Tsung-Yung Chang , Kevin Zhang , Fatih Hamzaoglu , Jonathan Shoemaker , Ming Huang
发明人： Stefan Rusu , Tsung-Yung Chang , Kevin Zhang , Fatih Hamzaoglu , Jonathan Shoemaker , Ming Huang
CPC分类号： G06F1/32 , G06F1/3287 , G11C11/417 , Y02D10/171
摘要： In one embodiment of the present invention, a technique is provided to control leakage of a cache sub-array. Other embodiments are disclosed herein. A sleep and shut-off circuit is connected between a virtual supply terminal and a first physical supply terminal to reduce leakage from the cache sub-array when the cache sub-array is disabled in a shut-off mode. The cache sub-array is connected between the virtual supply terminal and a second physical supply terminal. An active circuit is connected to the sleep and shut-off circuit in parallel to enable the cache sub-array in a normal mode and to disable the cache sub-array in the shut-off mode.
摘要翻译： 在本发明的一个实施例中，提供了一种用于控制高速缓存子阵列的泄漏的技术。 本文公开了其它实施例。 睡眠和关闭电路连接在虚拟供应终端和第一物理供应终端之间，以便在关闭模式下禁用高速缓存子阵列时减少从高速缓存子阵列的泄漏。 高速缓存子阵列连接在虚拟供电终端和第二物理供应终端之间。 有源电路并联连接到睡眠和关闭电路，以使高速缓存子阵列处于正常模式，并在关闭模式下禁用高速缓存子阵列。
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公开(公告)号：US20090300413A1
公开(公告)日：2009-12-03
申请号：US12540602
申请日：2009-08-13
CPC分类号： G11C29/52 , G06F11/1024 , G11C29/88 , G11C29/883 , G11C2029/0409
摘要： An apparatus and methods are disclosed herein for identifying and avoiding attempts to access a defective portion of memory. Errors associated with portions of memory, such as a cache memory, are tracked over time enabling detection of both hard and erratic errors. Based on the number of errors tracked over time for a portion of memory, it is determined if the portion of memory is defective. In response to determining portion of memory is defective, the portion of memory is disabled. The portion of memory may be flushed and moved before being disable. Additionally, disabling the portion of memory may be conditioned upon determining if it is allowable to disable the portion of memory.
摘要翻译： 本文公开了一种用于识别和避免访问存储器的缺陷部分的尝试的装置和方法。 与存储器部分相关联的错误（如高速缓冲存储器）随时间被跟踪，从而能够检测到错误和错误的错误。 基于存储器的一部分随时间跟踪的错误的数量，确定存储器的部分是否有缺陷。 响应于存储器的确定部分有缺陷，存储器的该部分被禁用。 存储器的一部分可能在禁用之前被刷新并移动。 此外，禁止部分存储器可以在确定是否允许禁用存储器部分的情况下进行调节。
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公开(公告)号：US20070005999A1
公开(公告)日：2007-01-04
申请号：US11174204
申请日：2005-06-30
申请人： Stefan Rusu , Tsung-Yung Chang , Kevin Zhang , Fatih Hamzaoglu , Jonathan Shoemaker , Ming Huang
发明人： Stefan Rusu , Tsung-Yung Chang , Kevin Zhang , Fatih Hamzaoglu , Jonathan Shoemaker , Ming Huang
IPC分类号： G06F1/00
CPC分类号： G06F1/32 , G06F1/3287 , G11C11/417 , Y02D10/171
摘要： In one embodiment of the present invention, a technique is provided to control leakage of a cache sub-array. Other embodiments are disclosed herein. A sleep and shut-off circuit is connected between a virtual supply terminal and a first physical supply terminal to reduce leakage from the cache sub-array when the cache sub-array is disabled in a shut-off mode. The cache sub-array is connected between the virtual supply terminal and a second physical supply terminal. An active circuit is connected to the sleep and shut-off circuit in parallel to enable the cache sub-array in a normal mode and to disable the cache sub-array in the shut-off mode.
摘要翻译： 在本发明的一个实施例中，提供了一种用于控制高速缓存子阵列的泄漏的技术。 本文公开了其它实施例。 睡眠和关闭电路连接在虚拟供应终端和第一物理供应终端之间，以便在关闭模式下禁用高速缓存子阵列时减少从高速缓存子阵列的泄漏。 高速缓存子阵列连接在虚拟供电终端和第二物理供应终端之间。 有源电路并联连接到睡眠和关闭电路，以使高速缓存子阵列处于正常模式，并在关闭模式下禁用高速缓存子阵列。
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