公开(公告)号：US20130047418A1

公开(公告)日：2013-02-28

申请号：US13568693

申请日：2012-08-07

申请人： Yang Je Lee ,  Gi Suk Kim ,  Joong Hyuk Jung ,  Dek Gin Yang

发明人： Yang Je Lee ,  Gi Suk Kim ,  Joong Hyuk Jung ,  Dek Gin Yang

IPC分类号： H05K3/02

CPC分类号： H05K3/0097 ,  H05K3/225 ,  H05K3/429 ,  H05K3/4652 ,  Y10T29/49004 ,  Y10T29/49155

摘要： The present invention discloses a method of manufacturing a multilayer PCB including: a panel preparation step of preparing a working panel on which a plurality of PCB units having a plurality of inner layer circuit pattern portions are arrayed; a defective portion removing step of removing a defective inner layer circuit pattern portion among the plurality of inner layer circuit pattern portions; a good portion providing step of providing a good inner layer circuit pattern portion in a portion of the working panel, from which the defective inner layer circuit pattern portion is removed; and an outer layer forming step of forming an outer layer circuit pattern portion in the PCB unit. The present invention is capable of improving productivity and reducing manufacturing costs by preventing product loss due to disposal of the PCB unit having the defective inner layer circuit pattern portion.

摘要翻译： 本发明公开了一种多层PCB的制造方法，其特征在于，包括：准备工作面板的面板准备工序，其上排列有多个内层电路图形部分的多个PCB单元; 去除所述多个内层电路图形部分中的有缺陷的内层电路图形部分的缺陷部分去除步骤; 良好的部分提供步骤，在工作面板的一部分中提供良好的内层电路图形部分，去除有缺陷的内层电路图案部分; 以及在PCB单元中形成外层电路图形部分的外层形成步骤。 本发明能够通过防止由于处理具有内层电路图形部分有缺陷的PCB单元而导致的产品损失，从而提高生产率并降低制造成本。