公开(公告)号：US20150178203A1

公开(公告)日：2015-06-25

申请号：US14140256

申请日：2013-12-24

申请人： Marc Torrant ,  Jorge E. Parra ,  Blaise Fanning ,  Joydeep Ray

发明人： Marc Torrant ,  Jorge E. Parra ,  Blaise Fanning ,  Joydeep Ray

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/123

摘要： Systems and methods for write allocation by a two-level memory controller. An example processing system comprises: a processing core; a memory controller communicatively coupled to the processing core; and a system memory communicatively coupled to the memory controller, the system memory comprising a first level memory and a second level memory; wherein the memory controller is configured, responsive to determining that a memory block referenced by a memory write request is not present in the first level memory, to allocate a new first level memory block without retrieving the memory block referenced by the request from the second level memory, wherein the memory write request is represented by an overwrite type memory write request.

摘要翻译： 由两级内存控制器进行写入分配的系统和方法。 一个示例处理系统包括：处理核心; 通信地耦合到所述处理核心的存储器控​​制器; 以及系统存储器，其通信地耦合到所述存储器控制器，所述系统存储器包括第一级存储器和第二级存储器; 其中，所述存储器控制器被配置为响应于确定由所述存储器写请求引用的存储器块不存在于所述第一级存储器中，以分配新的第一级存储器块而不从所述第二级检索由所述请求引用的所述存储器块 存储器，其中存储器写入请求由覆盖型存储器写入请求表示。

公开(公告)号：US20150082002A1

公开(公告)日：2015-03-19

申请号：US14031398

申请日：2013-09-19

申请人： Jorge E. Parra ,  Joydeep Ray ,  Ramadass Nagarajan

发明人： Jorge E. Parra ,  Joydeep Ray ,  Ramadass Nagarajan

IPC分类号： G06F12/10

CPC分类号： H04L9/3242 ,  G06F12/0607 ,  G06F13/16

摘要： Dynamic heterogeneous hashing function technology for balancing memory requests between multiple memory channels is described. A processor includes functional units and multiple memory channels, and a memory controller unit (MCU) coupled between them. The MCU includes a dynamic heterogeneous hashing module (DHHM) that includes multiple specific-purpose hashing function blocks that define different interleaving sequences for memory requests to alternately access the multiple memory channels. The DHHM also includes a hashing-function selection block. The hashing-function selection block is operable to identify a requesting functional unit originating a current memory request and to select one of the specific-purpose hashing function blocks for the current memory request in view of the requesting functional unit.

摘要翻译： 描述了用于平衡多个存储器通道之间的存储器请求的动态异构散列函数技术。 处理器包括功能单元和多个存储器通道，以及耦合在它们之间的存储器控​​制器单元（MCU）。 MCU包括动态异构散列模块（DHHM），其包括多个特定目的散列功能块，其定义用于交替访问多个存储器通道的存储器请求的不同交错序列。 DHHM还包括散列函数选择块。 散列函数选择块可用于识别发起当前存储器请求的请求功能单元，并根据请求功能单元选择当前存储器请求的特定目的散列功能块之一。

公开(公告)号：US09032099B1

公开(公告)日：2015-05-12

申请号：US14104260

申请日：2013-12-12

申请人： Jorge E. Parra ,  Marc Torrant ,  Joydeep Ray

发明人： Jorge E. Parra ,  Marc Torrant ,  Joydeep Ray

IPC分类号： G06F3/06 ,  G06F12/08 ,  G06F13/38 ,  G06F5/00

CPC分类号： G06F12/0804 ,  G06F12/08 ,  Y02D10/13

摘要： Multi-level memory architecture technologies are described. One processor includes a requesting unit, a first memory interface to couple to a far memory (FM), a second memory interface to couple to a near memory (NM) and a multi-level memory controller (MLMC) coupled to the requesting unit, the first memory interface and the second memory interface. The MLMC is to write data into a memory page of NM in response to a request from the requesting unit to retrieve the memory page from FM. The MLMC receives a hint from the requesting unit and clears a writeback bit for the memory page indicated in the hint. The hint indicates that the data contained in the memory page of the NM is not to be subsequently requested by the requesting unit. The MLMC starts a writeback operation of a memory sector including the memory page and one or more additional memory pages. The writeback operation is to transfer the data contained in the memory page from the NM to the FM when the writeback bit is set and the writeback operation does is not to transfer the data contained in the memory page from NM to the FM when the writeback bit is cleared.

摘要翻译： 描述了多层内存架构技术。 一个处理器包括请求单元，耦合到远存储器（FM）的第一存储器接口，耦合到接近存储器（NM）的第二存储器接口和耦合到请求单元的多级存储器控制器（MLMC） 第一个存储器接口和第二个存储器接口。 MLMC将响应于请求单元从FM获取存储器页面的请求将数据写入NM的存储器页面。 MLMC从请求单元接收提示，并清除提示中指示的内存页的回写位。 提示表明，NM的存储器页面中所包含的数据不会随后由请求单元请求。 MLMC启动包括存储器页面和一个或多个附加存储器页面的存储器扇区的回写操作。 回读操作是当写回位被设置时将存储器页面中包含的从NM的数据传送到FM，并且当回写位被写回时，回写操作确实不会将包含在存储器页面中的数据从NM传送到FM 被清除

公开(公告)号：US09424209B2

公开(公告)日：2016-08-23

申请号：US14031398

申请日：2013-09-19

申请人： Jorge E. Parra ,  Joydeep Ray ,  Ramadass Nagarajan

发明人： Jorge E. Parra ,  Joydeep Ray ,  Ramadass Nagarajan

IPC分类号： G06F12/00 ,  G06F13/16 ,  G06F12/06

CPC分类号： H04L9/3242 ,  G06F12/0607 ,  G06F13/16

摘要： Dynamic heterogeneous hashing function technology for balancing memory requests between multiple memory channels is described. A processor includes functional units and multiple memory channels, and a memory controller unit (MCU) coupled between them. The MCU includes a dynamic heterogeneous hashing module (DHHM) that includes multiple specific-purpose hashing function blocks that define different interleaving sequences for memory requests to alternately access the multiple memory channels. The DHHM also includes a hashing-function selection block. The hashing-function selection block is operable to identify a requesting functional unit originating a current memory request and to select one of the specific-purpose hashing function blocks for the current memory request in view of the requesting functional unit.

摘要翻译： 描述了用于平衡多个存储器通道之间的存储器请求的动态异构散列函数技术。 处理器包括功能单元和多个存储器通道，以及耦合在它们之间的存储器控​​制器单元（MCU）。 MCU包括动态异构散列模块（DHHM），其包括多个特定目的散列功能块，其定义用于交替访问多个存储器通道的存储器请求的不同交错序列。 DHHM还包括散列函数选择块。 散列函数选择块可用于识别发起当前存储器请求的请求功能单元，并根据请求功能单元选择当前存储器请求的特定目的散列功能块之一。