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    Writeback mechanisms for improving far memory utilization in multi-level memory architectures
    1.
    发明授权
    Writeback mechanisms for improving far memory utilization in multi-level memory architectures 有权
    用于改善多级内存架构中远程内存利用率的回写机制

    公开(公告)号：US09032099B1

    公开(公告)日：2015-05-12

    申请号：US14104260

    申请日：2013-12-12

    申请人： Jorge E. Parra ,  Marc Torrant ,  Joydeep Ray

    发明人： Jorge E. Parra ,  Marc Torrant ,  Joydeep Ray

    IPC分类号： G06F3/06 ,  G06F12/08 ,  G06F13/38 ,  G06F5/00

    CPC分类号： G06F12/0804 ,  G06F12/08 ,  Y02D10/13

    摘要： Multi-level memory architecture technologies are described. One processor includes a requesting unit, a first memory interface to couple to a far memory (FM), a second memory interface to couple to a near memory (NM) and a multi-level memory controller (MLMC) coupled to the requesting unit, the first memory interface and the second memory interface. The MLMC is to write data into a memory page of NM in response to a request from the requesting unit to retrieve the memory page from FM. The MLMC receives a hint from the requesting unit and clears a writeback bit for the memory page indicated in the hint. The hint indicates that the data contained in the memory page of the NM is not to be subsequently requested by the requesting unit. The MLMC starts a writeback operation of a memory sector including the memory page and one or more additional memory pages. The writeback operation is to transfer the data contained in the memory page from the NM to the FM when the writeback bit is set and the writeback operation does is not to transfer the data contained in the memory page from NM to the FM when the writeback bit is cleared.

    摘要翻译： 描述了多层内存架构技术。 一个处理器包括请求单元，耦合到远存储器（FM）的第一存储器接口，耦合到接近存储器（NM）的第二存储器接口和耦合到请求单元的多级存储器控制器（MLMC） 第一个存储器接口和第二个存储器接口。 MLMC将响应于请求单元从FM获取存储器页面的请求将数据写入NM的存储器页面。 MLMC从请求单元接收提示，并清除提示中指示的内存页的回写位。 提示表明，NM的存储器页面中所包含的数据不会随后由请求单元请求。 MLMC启动包括存储器页面和一个或多个附加存储器页面的存储器扇区的回写操作。 回读操作是当写回位被设置时将存储器页面中包含的从NM的数据传送到FM，并且当回写位被写回时，回写操作确实不会将包含在存储器页面中的数据从NM传送到FM 被清除

    OPTIMIZED WRITE ALLOCATION FOR TWO-LEVEL MEMORY
    2.
    发明申请
    OPTIMIZED WRITE ALLOCATION FOR TWO-LEVEL MEMORY 审中-公开
    两级记忆的优化写入分配

    公开(公告)号：US20150178203A1

    公开(公告)日：2015-06-25

    申请号：US14140256

    申请日：2013-12-24

    申请人： Marc Torrant ,  Jorge E. Parra ,  Blaise Fanning ,  Joydeep Ray

    发明人： Marc Torrant ,  Jorge E. Parra ,  Blaise Fanning ,  Joydeep Ray

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0811 ,  G06F12/123

    摘要： Systems and methods for write allocation by a two-level memory controller. An example processing system comprises: a processing core; a memory controller communicatively coupled to the processing core; and a system memory communicatively coupled to the memory controller, the system memory comprising a first level memory and a second level memory; wherein the memory controller is configured, responsive to determining that a memory block referenced by a memory write request is not present in the first level memory, to allocate a new first level memory block without retrieving the memory block referenced by the request from the second level memory, wherein the memory write request is represented by an overwrite type memory write request.

    摘要翻译： 由两级内存控制器进行写入分配的系统和方法。 一个示例处理系统包括：处理核心; 通信地耦合到所述处理核心的存储器控​​制器; 以及系统存储器，其通信地耦合到所述存储器控制器，所述系统存储器包括第一级存储器和第二级存储器; 其中，所述存储器控制器被配置为响应于确定由所述存储器写请求引用的存储器块不存在于所述第一级存储器中，以分配新的第一级存储器块而不从所述第二级检索由所述请求引用的所述存储器块 存储器，其中存储器写入请求由覆盖型存储器写入请求表示。

    Dynamic heterogeneous hashing functions in ranges of system memory addressing space
    3.
    发明授权
    Dynamic heterogeneous hashing functions in ranges of system memory addressing space 有权
    系统内存寻址空间范围内的动态异构散列函数

    公开(公告)号：US09424209B2

    公开(公告)日：2016-08-23

    申请号：US14031398

    申请日：2013-09-19

    申请人： Jorge E. Parra ,  Joydeep Ray ,  Ramadass Nagarajan

    发明人： Jorge E. Parra ,  Joydeep Ray ,  Ramadass Nagarajan

    IPC分类号： G06F12/00 ,  G06F13/16 ,  G06F12/06

    CPC分类号： H04L9/3242 ,  G06F12/0607 ,  G06F13/16

    摘要： Dynamic heterogeneous hashing function technology for balancing memory requests between multiple memory channels is described. A processor includes functional units and multiple memory channels, and a memory controller unit (MCU) coupled between them. The MCU includes a dynamic heterogeneous hashing module (DHHM) that includes multiple specific-purpose hashing function blocks that define different interleaving sequences for memory requests to alternately access the multiple memory channels. The DHHM also includes a hashing-function selection block. The hashing-function selection block is operable to identify a requesting functional unit originating a current memory request and to select one of the specific-purpose hashing function blocks for the current memory request in view of the requesting functional unit.

    摘要翻译： 描述了用于平衡多个存储器通道之间的存储器请求的动态异构散列函数技术。 处理器包括功能单元和多个存储器通道，以及耦合在它们之间的存储器控​​制器单元（MCU）。 MCU包括动态异构散列模块（DHHM），其包括多个特定目的散列功能块，其定义用于交替访问多个存储器通道的存储器请求的不同交错序列。 DHHM还包括散列函数选择块。 散列函数选择块可用于识别发起当前存储器请求的请求功能单元，并根据请求功能单元选择当前存储器请求的特定目的散列功能块之一。

    DYNAMIC HETEROGENEOUS HASHING FUNCTIONS IN RANGES OF SYSTEM MEMORY ADDRESSING SPACE
    4.
    发明申请
    DYNAMIC HETEROGENEOUS HASHING FUNCTIONS IN RANGES OF SYSTEM MEMORY ADDRESSING SPACE 有权
    系统记忆空间范围内的动态异质冲击函数

    公开(公告)号：US20150082002A1

    公开(公告)日：2015-03-19

    申请号：US14031398

    申请日：2013-09-19

    申请人： Jorge E. Parra ,  Joydeep Ray ,  Ramadass Nagarajan

    发明人： Jorge E. Parra ,  Joydeep Ray ,  Ramadass Nagarajan

    IPC分类号： G06F12/10

    CPC分类号： H04L9/3242 ,  G06F12/0607 ,  G06F13/16

    摘要： Dynamic heterogeneous hashing function technology for balancing memory requests between multiple memory channels is described. A processor includes functional units and multiple memory channels, and a memory controller unit (MCU) coupled between them. The MCU includes a dynamic heterogeneous hashing module (DHHM) that includes multiple specific-purpose hashing function blocks that define different interleaving sequences for memory requests to alternately access the multiple memory channels. The DHHM also includes a hashing-function selection block. The hashing-function selection block is operable to identify a requesting functional unit originating a current memory request and to select one of the specific-purpose hashing function blocks for the current memory request in view of the requesting functional unit.

    摘要翻译： 描述了用于平衡多个存储器通道之间的存储器请求的动态异构散列函数技术。 处理器包括功能单元和多个存储器通道，以及耦合在它们之间的存储器控​​制器单元（MCU）。 MCU包括动态异构散列模块（DHHM），其包括多个特定目的散列功能块，其定义用于交替访问多个存储器通道的存储器请求的不同交错序列。 DHHM还包括散列函数选择块。 散列函数选择块可用于识别发起当前存储器请求的请求功能单元，并根据请求功能单元选择当前存储器请求的特定目的散列功能块之一。

    ISOCHRONOUS AGENT DATA PINNING IN A MULTI-LEVEL MEMORY SYSTEM
    5.
    发明申请
    ISOCHRONOUS AGENT DATA PINNING IN A MULTI-LEVEL MEMORY SYSTEM 有权
    在多级存储器系统中的异步代理数据引导

    公开(公告)号：US20150169439A1

    公开(公告)日：2015-06-18

    申请号：US14133097

    申请日：2013-12-18

    申请人： Marc Torrant ,  David Puffer ,  Blaise Fanning ,  Bryan White ,  Joydeep Ray ,  Neil Schaper ,  Todd Witter ,  Altug Koker ,  Aditya Sreenivas

    发明人： Marc Torrant ,  David Puffer ,  Blaise Fanning ,  Bryan White ,  Joydeep Ray ,  Neil Schaper ,  Todd Witter ,  Altug Koker ,  Aditya Sreenivas

    IPC分类号： G06F12/02 ,  G06F12/08 ,  G06F12/10

    CPC分类号： G06F12/126

    摘要： A processing device comprises an instruction execution unit, a memory agent and pinning logic to pin memory pages in a multi-level memory system upon request by the memory agent. The pinning logic includes an agent interface module to receive, from the memory agent, a pin request indicating a first memory page in the multi-level memory system, the multi-level memory system comprising a near memory and a far memory. The pinning logic further includes a memory interface module to retrieve the first memory page from the far memory and write the first memory page to the near memory. In addition, the pinning logic also includes a descriptor table management module to mark the first memory page as pinned in the near memory, wherein marking the first memory page as pinned comprises setting a pinning bit corresponding to the first memory page in a cache descriptor table and to prevent the first memory page from being evicted from the near memory when the first memory page is marked as pinned.

    摘要翻译： 处理设备包括指令执行单元，存储器代理和钉住逻辑，以在存储器请求时针对多级存储器系统中的存储器页面进行引脚。 钉扎逻辑包括代理接口模块，用于从存储器代理接收指示多级存储器系统中的第一存储器页的引脚请求，所述多级存储器系统包括近存储器和远存储器。 钉扎逻辑还包括存储器接口模块，用于从远端存储器检索第一存储器页面，并将第一存储器页面写入近端存储器。 此外，钉扎逻辑还包括描述符表管理模块，用于将第一存储器页标记为固定在近存储器中，其中将第一存储器页标记为固定包括将对应于第一存储器页的锁存位设置在高速缓存描述符表中 并且当第一存储器页面被标记为被固定时，防止第一存储器页被从近存储器逐出。