公开(公告)号：US5894578A

公开(公告)日：1999-04-13

申请号：US575685

申请日：1995-12-19

申请人： Qadeer A. Qureshi ,  Joseph A. Bailey ,  Dan S. Mudgett

发明人： Qadeer A. Qureshi ,  Joseph A. Bailey ,  Dan S. Mudgett

IPC分类号： G06F13/24 ,  G06F9/46

CPC分类号： G06F13/24

摘要： A programmable interrupt controller for use in computer systems including one or more CPUs is provided. The programmable interrupt controller includes an interrupt request interface, a central interrupt controller, random access memory, and at least one processor interface. The central interrupt controller systematically selects interrupt requests from the interrupt request interface. Information associated with each interrupt request is stored in the random access memory. The central interrupt controller access the information in the random access memory and uses the information and the state of the currently selected interrupt request to determine a next state for the currently selected interrupt request. The information is passed on to the processor interface to determine when and if the interrupt request should issue to one of the CPUs.

摘要翻译： 提供了一种用于包括一个或多个CPU的计算机系统的可编程中断控制器。 可编程中断控制器包括中断请求接口，中央中断控制器，随机存取存储器和至少一个处理器接口。 中央中断控制器系统地从中断请求接口中选择中断请求。 与每个中断请求相关联的信息存储在随机存取存储器中。 中央中断控制器访问随机存取存储器中的信息，并使用当前选择的中断请求的信息和状态来确定当前选择的中断请求的下一状态。 该信息被传递到处理器接口，以确定中断请求何时以及是否向其中一个CPU发布。

公开(公告)号：US5892956A

公开(公告)日：1999-04-06

申请号：US934261

申请日：1997-09-19

申请人： Qadeer A. Qureshi ,  Joseph A. Bailey ,  Dan S. Mudgett

发明人： Qadeer A. Qureshi ,  Joseph A. Bailey ,  Dan S. Mudgett

IPC分类号： G06F9/46 ,  G06F13/26

CPC分类号： G06F13/26

摘要： A programmable interrupt controller for use in a multiprocessing environment that can support a serial bus to send interrupt information to the processors. The interrupt serial bus has a data line to drive all the interrupt information to all the processors and a clock line to synchronize edges for the data stream. A third line, normally tri-stated, may be used to provide a parity error indication for the serial bus. The serial data includes a processor identification, a pin identification and state information. As the programmable interrupt controller sends the interrupt data on the serial bus, all the processors clock the data and check parity. If a processor finds a parity error, it drives the parity error indication low so that the information may be transmitted again. No processor will execute the command contained in the serial message before the time has elapsed for any of the processors to report a parity error. If there is no parity error, the processor accepts and decodes the message and asserts or deasserts the appropriate signal.

摘要翻译： 一种用于多处理环境的可编程中断控制器，可以支持串行总线向处理器发送中断信息。 中断串行总线具有数据线，用于将所有中断信息驱动到所有处理器和时钟线以同步数据流的边沿。 通常三通道的第三行可用于为串行总线提供奇偶校验错误指示。 串行数据包括处理器标识，引脚标识和状态信息。 由于可编程中断控制器在串行总线上发送中断数据，所有的处理器都会对数据进行计时并检查奇偶校验。 如果处理器发现奇偶校验错误，则将奇偶校验错误指示值驱动为低，以便再次发送信息。 没有处理器将在任何处理器报告奇偶校验错误的时间过去之前执行包含在串行消息中的命令。 如果没有奇偶校验错误，则处理器接受并解码消息，并声明或取消对相应信号的声明。

公开(公告)号：US5557769A

公开(公告)日：1996-09-17

申请号：US261242

申请日：1994-06-17

申请人： Joseph A. Bailey ,  Steve L. Belt

发明人： Joseph A. Bailey ,  Steve L. Belt

IPC分类号： G06F12/08

CPC分类号： G06F12/0835

摘要： An integrated processor includes CPU core, cache memory, and cache controller coupled to a local bus via a local bus interface. The integrated processor further includes memory controller for coupling system memory to the local bus, and a bus interface unit for coupling external peripheral devices to the local bus. The cache controller includes an address tag and state logic circuit which keeps track of a physical address in system memory which corresponds to each entry within cache memory. Address tag and state logic circuit contains state information that indicates whether each cache line is valid and/or dirty. The cache controller includes a snoop control circuit which monitors the local bus to determine whether a memory cycle has been executed by an alternate bus master. During such a memory cycle of an alternate bus master, a comparator circuit determines whether a cache hit has occurred. If a cache read hit occurs with respect to a dirty cache line, the cache controller asserts an inhibit signal which causes the memory controller to ignore the cycle. The read request is instead serviced by the cache controller by providing the requested data from the cache memory to local bus 112. If a cache write operation occurs, data is written into the system memory via system memory controller, and the data is concurrently latched into the corresponding line of the cache memory. The status of cache line may further be updated to clean if the data transfer encompassed a complete cache line.

摘要翻译： 集成处理器包括经由本地总线接口耦合到本地总线的CPU内核，高速缓冲存储器和高速缓存控制器。 集成处理器还包括用于将系统存储器耦合到本地总线的存储器控​​制器，以及用于将外部外围设备耦合到本地总线的总线接口单元。 高速缓存控制器包括地址标签和状态逻辑电路，其跟踪与高速缓冲存储器内的每个条目对应的系统存储器中的物理地址。 地址标签和状态逻辑电路包含指示每个高速缓存行是否有效和/或脏的状态信息。 高速缓存控制器包括一个监视控制电路，监视本地总线，以确定一个存储器周期是否由一个备用总线主机执行。 在替代总线主机的这种存储周期期间，比较器电路确定是否发生了高速缓存命中。 如果相对于脏高速缓存线发生缓存读取命中，则高速缓存控制器断言禁止信号，这导致存储器控制器忽略该周期。 读取请求由高速缓存控制器通过从缓存存储器向本地总线112提供所请求的数据而被服务。如果发生高速缓存写入操作，则通过系统存储器控制器将数据写入系统存储器，并且数据被同时锁存 高速缓存的相应行。 如果数据传输包含完整的高速缓存行，则可以进一步更新高速缓存行的状态以进行清理。

公开(公告)号：US861088A

公开(公告)日：1907-07-23

申请号：US1906330182

申请日：1906-08-11

申请人： JOSEPH A BAILEY ,  CHANDLER ORVIN H

发明人： CHANDLER ORVIN H

CPC分类号： E06B7/084

公开(公告)号：US06742075B1

公开(公告)日：2004-05-25

申请号：US09998187

申请日：2001-12-03

申请人： Joseph A. Bailey ,  Joseph Winkles

发明人： Joseph A. Bailey ,  Joseph Winkles

IPC分类号： G06F1336

CPC分类号： G06F13/14

摘要： A host channel adapter is configured for servicing a work notification, supplied by a host process to an assigned destination address accessable by the host channel adapter, based on matching the assigned destination address with a stored notification address from one of a plurality of queue pair context entries stored within the host channel adapter. The host channel adapter receives a queue pair context entry including a notification address, based on creation of a corresponding queue pair for a host process. The queue pair enables the host process to post a work descriptor and output a work notification to the host channel adapter by writing the work notification to an assigned destination address. The host channel adapter matches the assigned destination address with a stored notification address, and services the work descriptor based on the corresponding queue pair attributes specified in the identified queue pair context entry.

摘要翻译： 主机通道适配器被配置为基于将所分配的目的地地址与从多个队列对上下文之一的存储的通知地址相匹配来将由主机进程提供的工作通知服务到由主机通道适配器可访问的分配的目的地地址 存储在主机通道适配器内的条目。 主机通道适配器基于为主机进程创建相应的队列对，接收包括通知地址的队列对上下文条目。 队列对使主机进程能够发布工作描述符，并通过将工作通知写入分配的目的地地址来向主机通道适配器输出工作通知。 主机通道适配器将分配的目的地地址与存储的通知地址相匹配，并且基于在所识别的队列对上下文条目中指定的对应的队列对属性来服务于工作描述符。

公开(公告)号：US5850558A

公开(公告)日：1998-12-15

申请号：US575664

申请日：1995-12-19

申请人： Qadeer A. Qureshi ,  Joseph A. Bailey ,  Dan S. Mudgett

发明人： Qadeer A. Qureshi ,  Joseph A. Bailey ,  Dan S. Mudgett

IPC分类号： G06F13/24 ,  G06F9/46

CPC分类号： G06F13/24

摘要： A programmable interrupt controller is provided for use in computer systems including one or more CPUs. The programmable interrupt controller includes an interrupt request interface, a storage device, and at least one processor interface having an interrupt nesting buffer. An unique interrupt identification code is assigned to each interrupt request and used to reference information in the storage device associated with each interrupt request. The interrupt request interface uses the unique interrupt identification code to access the information for each interrupt request and determine if the interrupt request should proceed to one of the processor interfaces. The processor interface uses the unique interrupt identification code to access the information in order to determine if and when the interrupt request should issue to one of the CPUs.

摘要翻译： 提供可编程中断控制器，用于包括一个或多个CPU的计算机系统。 可编程中断控制器包括中断请求接口，存储设备以及具有中断嵌套缓冲器的至少一个处理器接口。 每个中断请求都分配唯一的中断识别码，用于引用与每个中断请求相关联的存储设备中的信息。 中断请求接口使用唯一的中断标识码来访问每个中断请求的信息，并确定中断请求是否应继续到其中一个处理器接口。 处理器接口使用唯一的中断识别码来访问信息，以确定中断请求是否和何时发送给其中一个CPU。

公开(公告)号：US5850555A

公开(公告)日：1998-12-15

申请号：US575683

申请日：1995-12-19

申请人： Qadeer A. Qureshi ,  Joseph A. Bailey ,  Dan S. Mudgett

发明人： Qadeer A. Qureshi ,  Joseph A. Bailey ,  Dan S. Mudgett

IPC分类号： G06F13/24 ,  G06F13/00 ,  G06F13/14

CPC分类号： G06F13/24

摘要： A programmable interrupt controller for use in computer systems including one or more CPUs is provided. The programmable interrupt controller includes an interrupt request interface, a validity checker, and at least one processor interface. The validity checker monitors the state of each interrupt request as it is processed through the interrupt controller. The interrupt request is canceled if the interrupt request becomes invalid. Alternatively, the programmable interrupt controller issues a spurious interrupt vector if the interrupt request becomes invalid after a CPU has responded.

摘要翻译： 提供了一种用于包括一个或多个CPU的计算机系统的可编程中断控制器。 可编程中断控制器包括中断请求接口，有效性检查器和至少一个处理器接口。 有效性检查器通过中断控制器来处理每个中断请求的状态。 如果中断请求无效，则中断请求被取消。 或者，如果中断请求在CPU响应后变为无效，则可编程中断控制器发出伪中断向量。

公开(公告)号：US5703919A

公开(公告)日：1997-12-30

申请号：US633671

申请日：1996-04-17

申请人： Joseph A. Bailey ,  Qadeer A. Qureshi

发明人： Joseph A. Bailey ,  Qadeer A. Qureshi

IPC分类号： G04G5/00 ,  G07C3/02

CPC分类号： G04G5/00

摘要： A method and apparatus for reading a timer with an asynchronous circuit. A computer system is provided having a system clock and an asynchronous timer clock. The computer system includes a counter clocking from the timer clock and a latch coupled to output of the counter. First logic, synchronized to the timer clock, is coupled to control the latch responsive to a control signal from the computer system. Second logic synchronized to the system clock and coupled to the first logic is configured to provide an indication to the computer system of when the system can read the latched data and be assured of its validity. The computer system will thereby be prevented from reading the timer before it has stabilized.

摘要翻译： 一种用异步电路读取定时器的方法和装置。 提供了具有系统时钟和异步定时器时钟的计算机系统。 计算机系统包括来自定时器时钟的计时器和耦合到计数器的输出的锁存器。 与定时器时钟同步的第一逻辑被耦合以响应于来自计算机系统的控制信号来控制锁存器。 与系统时钟同步并耦合到第一逻辑的第二逻辑被配置为向计算机系统提供系统何时读取锁存的数据并确保其有效性的指示。 因此，计算机系统在其稳定之前将被阻止读取定时器。

公开(公告)号：US07292593B1

公开(公告)日：2007-11-06

申请号：US10107151

申请日：2002-03-28

申请人： Joseph Winkles ,  Joseph A. Bailey

发明人： Joseph Winkles ,  Joseph A. Bailey

IPC分类号： H04L12/28 ,  H04L12/56 ,  H04J3/16

CPC分类号： H04L12/66

摘要： A host channel adapter includes a transport layer module, a link layer module, and buffer memory having memory portions configured for storage of transmit data packets output by the transport layer module for transmission by the link layer module on identified virtual lanes. The transport layer module is configured for identifying a virtual lane for each transmit data packet, and for storing the transmit data packet in the corresponding memory portion assigned to the corresponding identified virtual lane. Hence, the transmit data packets output by the transport layer module are stored in the memory portions based on their respective identified virtual lanes, where each memory portion stores the transmit data packets for the corresponding identified virtual lane. The link layer module retrieves the transmit data packets from a selected memory portion corresponding to a currently-serviced virtual lane based on a prescribed virtual lane arbitration. Hence, the link layer module can retrieve the transmit data packets for the currently-serviced virtual lane with minimal processing, based on accessing the corresponding memory portion.

摘要翻译： 主机通道适配器包括传输层模块，链路层模块和缓冲存储器，其具有被配置用于存储由传输层模块输出的传输数据分组的链路层模块在所识别的虚拟通道上传输的存储器部分。 传输层模块被配置用于识别每个发送数据分组的虚拟通道，并且用于将发送数据分组存储在分配给相应识别的虚拟通道的相应存储器部分中。 因此，传输层模块输出的发送数据分组基于它们各自识别的虚拟通道存储在存储器部分中，其中每个存储器部分存储用于相应识别的虚拟通道的发送数据分组。 链路层模块基于规定的虚拟通道仲裁从与当前服务的虚拟通道相对应的选择的存储器部分检索发送数据分组。 因此，基于访问对应的存储器部分，链路层模块可以以最少的处理来检索用于当前服务的虚拟通道的发送数据分组。

公开(公告)号：US07209489B1

公开(公告)日：2007-04-24

申请号：US10052459

申请日：2002-01-23

申请人： Joseph A. Bailey ,  Joseph Winkles ,  Norman Hack ,  Bahadir Erimli

发明人： Joseph A. Bailey ,  Joseph Winkles ,  Norman Hack ,  Bahadir Erimli

IPC分类号： H04L12/28 ,  H04J3/16 ,  G06F3/00

CPC分类号： H04L47/10 ,  H04L47/2425 ,  H04L47/34

摘要： A host channel adapter is configured for servicing received work notifications based on identifying the work notifications associated with the virtual lanes (VL) having a prescribed ordering position identified by the link layer operations. The host channel adapter, in response to receiving a work notification for a prescribed service level (SL), determines the virtual lane associated with the specified service level based on a prescribed service level to virtual lane mapping. If necessary (e.g., for an unreliable datagram service type), the work notification supplies the prescribed service level (SL) for the host channel adapter. The host channel adapter also determines an ordering position for the determined virtual lane from the link layer module, and selectively services the work notification based on the corresponding ordering position.

摘要翻译： 主机通道适配器被配置为基于识别与具有由链路层操作所标识的规定排序位置的虚拟通道（VL）相关联的工作通知来服务接收到的工作通知。 主机通道适配器响应于接收到规定服务级别（SL）的工作通知，基于规定的服务级别到虚拟通道映射来确定与指定服务级别相关联的虚拟通道。 如果需要（例如，对于不可靠的数据报服务类型），工作通知提供用于主机通道适配器的规定服务级别（SL）。 主机通道适配器还确定来自链路层模块的所确定的虚拟通道的排序位置，并且基于相应的排序位置选择性地服务工作通知。