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    TCP control packet differential service
    4.
    发明授权
    TCP control packet differential service 有权
    TCP控制包差分服务

    公开(公告)号：US07366168B2

    公开(公告)日：2008-04-29

    申请号：US09824241

    申请日：2001-04-03

    申请人： Mark A Hughes ,  Daniel M O'Keeffe ,  Kevin Loughran ,  Joseph N Butler

    发明人： Mark A Hughes ,  Daniel M O'Keeffe ,  Kevin Loughran ,  Joseph N Butler

    IPC分类号： H04L12/56

    CPC分类号： H04L47/193 ,  H04L47/10 ,  H04L47/125 ,  H04L47/2433

    摘要： A method and switch for controlling the allocation of priority of TCP packets, more particularly for distinguishing between data and control packets and assigning an increased priority to control packets. The layer 4 information in the form of the flag bits of the header are snooped in the switch to determine whether any flag other than PSH is set and if so to allocate a priority to that packet, which will usually be a higher priority than data packets.

    摘要翻译： 一种用于控制TCP分组的优先级分配的方法和开关，更具体地说是用于区分数据和控制分组，并且将增加的优先级分配给控制分组。 标头中标志位形式的层4信息被窥探在交换机中，以确定是否设置了除PSH之外的任何标志，如果是，则为该分组分配优先级，这通常比数据包更高优先级 。

    On-chip detection of clock gitches by examination of consecutive data
    5.
    发明授权
    On-chip detection of clock gitches by examination of consecutive data 失效
    通过检查连续数据片上检测时钟接头

    公开(公告)号：US06543027B1

    公开(公告)日：2003-04-01

    申请号：US09671121

    申请日：2000-09-28

    申请人： Mark A Hughes ,  Joseph N Butler ,  Neil O Fanning

    发明人： Mark A Hughes ,  Joseph N Butler ,  Neil O Fanning

    IPC分类号： G06F1100

    CPC分类号： G11C7/1018 ,  G11C7/1072 ,  G11C29/14

    摘要： An application specific integrated circuit includes a clock recovery circuit which recovers from an input signal a repetitive sequence of data values wherein no two consecutive values are the same and a recovered clock. An address generator responds to the recovered clock to cause storage of the data values in said memory in a set of locations having addresses generated by the address generator, so that the address generated by the generator increments in response to a repetitive transition in the recovered clock. The existence of a clock glitch is found by reading the data values from the set of locations to determine whether any two consecutive locations contain the same data value.

    摘要翻译： 专用集成电路包括时钟恢复电路，其从输入信号中恢复其中没有两个连续值相同的数据值的重复序列和恢复的时钟。 地址发生器响应于恢复的时钟，以使得存储器中的数据值存储在具有由地址发生器产生的地址的一组位置中，使得由发生器产生的地址响应于恢复的时钟中的重复转换而递增 。 通过读取位置集合中的数据值来确定是否有任何两个连续的位置包含相同的数据值来发现存在时钟毛刺。

    High speed parallel bit error rate tester
    6.
    发明授权
    High speed parallel bit error rate tester 失效
    高速并行位错误率测试仪

    公开(公告)号：US06438717B1

    公开(公告)日：2002-08-20

    申请号：US09436350

    申请日：1999-11-09

    申请人： Joseph N Butler ,  Mark A Hughes ,  Neil O Fanning ,  Eugene O'Neill ,  Una Quinlan

    发明人： Joseph N Butler ,  Mark A Hughes ,  Neil O Fanning ,  Eugene O'Neill ,  Una Quinlan

    IPC分类号： G06F1100

    CPC分类号： H04L1/20 ,  H04L1/0001 ,  H04L25/14

    摘要： A high speed link between chips and comprising a multiplicity of synchronous serial data channels includes an onboard detector for detecting an error rate for each channel. The transmitter and the receiver chips are configured in response to the detector to select the channel having the lowest error rate as the control channel and optionally to render at least the channel with the highest error rate inactive.

    摘要翻译： 芯片之间的高速链路包括多个同步串行数据信道，包括用于检测每个信道的错误率的板上检测器。 响应于检测器配置发射机和接收机芯片，以选择具有最低误码率的信道作为控制信道，并且可选地使至少具有最高错误率的信道无效。