公开(公告)号：US20240344636A1

公开(公告)日：2024-10-17

申请号：US18510824

申请日：2023-11-16

申请人： JOSEPH RUTKOWSKI

发明人： JOSEPH RUTKOWSKI

IPC分类号： F16L3/04 ,  F16L3/06 ,  H02G3/04

CPC分类号： F16L3/04 ,  F16L3/06 ,  H02G3/0456

摘要： Presented is a data cable retaining post for retaining data cable laid along a ladder rack having a pair of longitudinal main supports, a first of the longitudinal main supports having an upper surface and a lower surface. The data cable retaining post includes a front plate and a connection member, the connection member having a lower portion forming a hook, a mid-portion forming a locking member, and an upper portion. When installed on the first of the longitudinal main supports of ladder rack, the lower portion of the connection member is adapted to be positioned with the hook surrounding the lower surface of the longitudinal main support and the mid-portion is adapted to be positioned adjacent the upper surface of the longitudinal main support such that the locking member locks the data cable retaining post to the longitudinal main support.

公开(公告)号：US07859314B2

公开(公告)日：2010-12-28

申请号：US12294982

申请日：2007-03-31

申请人： Joseph Rutkowski ,  Alma Anderson

发明人： Joseph Rutkowski ,  Alma Anderson

IPC分类号： H03B1/00

CPC分类号： H03K19/00361 ,  H03K17/166

摘要： Edge-rate control circuits and methods are implemented using a variety of arrangements and methods. Using one such method, an output signal of a bus is controlled by decoupling a feedback capacitor (116) from a gate of a transistor (108) using an isolation switch (106). The transistor (108) is used to control the output signal. A predetermined amount of charge is removed from the feedback capacitor (116) using a charge distribution capacitor (114) that is selectively coupled to the feedback capacitor (116) using a switch (112). The switch (112) is enabled in response to the output signal reaching an output voltage and disabled in response to the charge distribution capacitor (114) reaching a reference voltage.

摘要翻译： 使用各种布置和方法实现边缘速率控制电路和方法。 使用一种这样的方法，通过使用隔离开关（106）使反馈电容器（116）与晶体管（108）的栅极去耦合来控制总线的输出信号。 晶体管（108）用于控制输出信号。 使用使用开关（112）选择性地耦合到反馈电容器（116）的电荷分配电容器（114），从反馈电容器（116）去除预定量的电荷。 开关（112）响应于输出信号达到输出电压而被使能，并且响应于电荷分配电容器（114）达到参考电压而被禁用。

公开(公告)号：US20100264970A1

公开(公告)日：2010-10-21

申请号：US12770793

申请日：2010-04-30

申请人： Alma ANDERSON ,  Joseph RUTKOWSKI ,  Dave OEHLER

发明人： Alma ANDERSON ,  Joseph RUTKOWSKI ,  Dave OEHLER

IPC分类号： H03K5/01

CPC分类号： H03K17/166

摘要： Consistent with an example embodiment, an edge-rate control circuit arrangement (300) for an I2C bus application comprises a first circuit stage (10, M1, M3), responsive to a state transition of a received signal. A second circuit stage (310, 25, 20, 35, 45, M4, ESD) is responsive to the state transition of the received signal and includes drive circuitry (M4) that is activated in response to the state transition of the received signal in order to provide an edge-transition signal for an I2C bus, and regulation circuitry (310, R1, R2, M0, M2) adapted to control the drive circuit and regulate a transition rate for the edge-transition signal, the transition rate being greater than a transition rate of the received signal at the first circuit stage and greater than a minimum and less than a maximum transition rate designated for communication on the I2C bus.

摘要翻译： 与示例实施例一致，用于I2C总线应用的边沿速率控制电路装置（300）包括响应于接收信号的状态转换的第一电路级（10，M1，M3）。 第二电路级（310,25,20,35,45,4H，M4，ESD）响应于接收信号的状态转换，并且包括响应于接收信号的状态转变而被激活的驱动电路（M4） 为了为I2C总线提供边沿转换信号，以及调节电路（310，R1，R2，M0，M2），适用于控制驱动电路并调节边沿转换信号的转换速率，转换速率更大 比第一电路级的接收信号的转换速率高大于最小值，小于指定用于在I2C总线上进行通信的最大转换速率。

公开(公告)号：US07733142B2

公开(公告)日：2010-06-08

申请号：US11816710

申请日：2006-02-24

申请人： Alma Anderson ,  Joseph Rutkowski ,  Dave Oehler

发明人： Alma Anderson ,  Joseph Rutkowski ,  Dave Oehler

IPC分类号： H03K5/12

CPC分类号： H03K17/166

摘要： Consistent with an example embodiment, an edge-rate control circuit arrangement (300) for an I2C bus application comprises a first circuit stage (10, M1, M3), responsive to a state transition of a received signal. A second circuit stage (310, 25, 20, 35, 45, M4, ESD) is responsive to the state transition of the received signal and includes drive circuitry (M4) that is activated in response to the state transition of the received signal in order to provide an edge-transition signal for an I2C bus, and regulation circuitry (310, R1, R2, M0, M2) adapted to control the drive circuit and regulate a transition rate for the edge-transition signal, the transition rate being greater than a transition rate of the received signal at the first circuit stage and greater than a minimum and less than a maximum transition rate designated for communication on the I2C bus.

摘要翻译： 与示例实施例一致，用于I2C总线应用的边沿速率控制电路装置（300）包括响应于接收信号的状态转换的第一电路级（10，M1，M3）。 第二电路级（310,25,20,35,45,4H，M4，ESD）响应于接收信号的状态转换，并且包括响应于接收信号的状态转变而被激活的驱动电路（M4） 为了为I2C总线提供边沿转换信号，以及调节电路（310，R1，R2，M0，M2），适用于控制驱动电路并调节边沿转换信号的转换速率，转换速率更大 比第一电路级的接收信号的转换速率高大于最小值，小于指定用于在I2C总线上进行通信的最大转换速率。

公开(公告)号：US20100237919A1

公开(公告)日：2010-09-23

申请号：US12294982

申请日：2007-03-31

申请人： Joseph Rutkowski ,  Alma Anderson

发明人： Joseph Rutkowski ,  Alma Anderson

IPC分类号： H03K5/12

CPC分类号： H03K19/00361 ,  H03K17/166

摘要： Edge-rate control circuits and methods are implemented using a variety of arrangements and methods. Using one such method, an output signal of a bus is controlled by decoupling a feedback capacitor (116) from a gate of a transistor (108) using an isolation switch (106). The transistor (108) is used to control the output signal. A predetermined amount of charge is removed from the feedback capacitor (116) using a charge distribution capacitor (114) that is selectively coupled to the feedback capacitor (116) using a switch (112). The switch (112) is enabled in response to the output signal reaching an output voltage and disabled in response to the charge distribution capacitor (114) reaching a reference voltage.

摘要翻译： 使用各种布置和方法实现边缘速率控制电路和方法。 使用一种这样的方法，通过使用隔离开关（106）将反馈电容器（116）与晶体管（108）的栅极去耦合来控制总线的输出信号。 晶体管（108）用于控制输出信号。 使用使用开关（112）选择性地耦合到反馈电容器（116）的电荷分配电容器（114），从反馈电容器（116）去除预定量的电荷。 开关（112）响应于输出信号达到输出电压而被使能，并且响应于电荷分配电容器（114）达到参考电压而被禁用。

公开(公告)号：US3635188A

公开(公告)日：1972-01-18

申请号：US3635188D

申请日：1969-08-08

申请人： JOSEPH RUTKOWSKI

发明人： RUTKOWSKI JOSEPH

IPC分类号： A63B35/12 ,  A63C11/10 ,  B63B35/00

CPC分类号： A63B35/12

摘要： An underwater propulsion device having a separate housing carrying a propulsion motor and a propeller adapted to be attached to a swimmer''s foot as by a shoe with power units, such as batteries or compressed gas carried by the swimmer and carrying a plurality of annular flotation rings around the periphery of the housing; the housing being hingedly attached to the swimmer''s shoe for allowing the swimmer to walk on the ocean bottom or other surfaces.

摘要翻译： 一种水下推进装置，其具有承载推进电动机和推进器的单独的壳体，其适于通过具有动力单元（例如由游泳者携带的电池或压缩气体）并且携带多个环形浮选环的动力单元（例如鞋）附接到游泳者的脚 外壳的外围; 该壳体铰接地连接到游泳者的鞋上，以允许游泳者在海底或其他表面上行走。

公开(公告)号：US07940102B2

公开(公告)日：2011-05-10

申请号：US12770793

申请日：2010-04-30

申请人： Alma Anderson ,  Joseph Rutkowski ,  Dave Oehler

发明人： Alma Anderson ,  Joseph Rutkowski ,  Dave Oehler

IPC分类号： H03K5/12

CPC分类号： H03K17/166

摘要： Consistent with an example embodiment, an edge-rate control circuit arrangement (300) for an I2C bus application comprises a first circuit stage (10, M1, M3), responsive to a state transition of a received signal. A second circuit stage (310, 25, 20, 35, 45, M4, ESD) is responsive to the state transition of the received signal and includes drive circuitry (M4) that is activated in response to the state transition of the received signal in order to provide an edge-transition signal for an I2C bus, and regulation circuitry (310, R1, R2, M0, M2) adapted to control the drive circuit and regulate a transition rate for the edge-transition signal, the transition rate being greater than a transition rate of the received signal at the first circuit stage and greater than a minimum and less than a maximum transition rate designated for communication on the I2C bus.

摘要翻译： 与示例实施例一致，用于I2C总线应用的边沿速率控制电路装置（300）包括响应于接收信号的状态转换的第一电路级（10，M1，M3）。 第二电路级（310,25,20,35,45,4H，M4，ESD）响应于接收信号的状态转换，并且包括响应于接收信号的状态转变而被激活的驱动电路（M4） 为了为I2C总线提供边沿转换信号，以及调节电路（310，R1，R2，M0，M2），适用于控制驱动电路并调节边沿转换信号的转换速率，转换速率更大 比第一电路级的接收信号的转换速率高大于最小值，小于指定用于在I2C总线上进行通信的最大转换速率。

公开(公告)号：US20090066381A1

公开(公告)日：2009-03-12

申请号：US11816710

申请日：2006-02-24

申请人： Alma Anderson ,  Joseph Rutkowski ,  Dave Oehler

发明人： Alma Anderson ,  Joseph Rutkowski ,  Dave Oehler

IPC分类号： H03K5/01

CPC分类号： H03K17/166

摘要： In an I2C bus, an edge rate control for an output slows the falling edge of a signal. In an example embodiment, there is an edge rate control circuit for use in an I2C bus. The circuit comprises a resistor divider having a first terminal, a divider terminal, and a second terminal. There is a first NMOS transistor having a source, drain, and gate terminal and a first PMOS transistor having a source, drain, and gate terminal; the source terminals of the first NMOS and first PMOS transistors are coupled to one another; the drain terminal of the first PMOS transistor is coupled to the divider terminal of the resistor divider; the gate of the first PMOS transistor is coupled to the second terminal of the resistor divider; and the drain of the first NMOS transistor is coupled to ground.

摘要翻译： 在I2C总线中，输出的边沿速率控制会降低信号的下降沿。 在示例实施例中，存在用于I2C总线的边沿速率控制电路。 该电路包括具有第一端子，分压器端子和第二端子的电阻器分压器。 存在具有源极，漏极和栅极端子的第一NMOS晶体管和具有源极，漏极和栅极端子的第一PMOS晶体管; 第一NMOS和第一PMOS晶体管的源极端子彼此耦合; 第一PMOS晶体管的漏极端子耦合到电阻分压器的除法器端子; 第一PMOS晶体管的栅极耦合到电阻分压器的第二端; 并且第一NMOS晶体管的漏极耦合到地。