公开(公告)号：US07979597B2

公开(公告)日：2011-07-12

申请号：US12761662

申请日：2010-04-16

申请人： Amrita Deshpande ,  Alma Anderson ,  Jean-Marc Irazabal ,  Stephen Blozis ,  Paul Boogaards

发明人： Amrita Deshpande ,  Alma Anderson ,  Jean-Marc Irazabal ,  Stephen Blozis ,  Paul Boogaards

IPC分类号： G06F3/00

CPC分类号： G06F13/4291

摘要： Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programming of parallel slave devices concurrently using an I2C serial bus. At least two slave devices are coupled in parallel on the data transfer bus and configured to load serial data over the serial data line using the communications protocol. Each slave device includes a programmable configuration register configured to be programmed, using the communications protocol, to select one of a plurality of selectable slave device configurations. One of the selectable slave device configurations causes the at least two slave devices to load the serial data in parallel, and another of the selectable slave device configurations causes the at least two slave devices to be loaded one at a time.

摘要翻译： 与一个示例性实施例一致，使用具有串行数据线的串行数据传输总线和用于实现通信协议的时钟线的通信系统使用I2C串行总线并行编程并行从设备。 至少两个从设备在数据传输总线上并联耦合，并配置为使用通信协议通过串行数据线加载串行数据。 每个从设备包括可编程配置寄存器，其被配置为使用通信协议来编程以选择多个可选择的从设备配置中的一个。 可选择的从设备配置之一使得至少两个从设备并行加载串行数据，另一个可选择的从设备配置使得至少两个从设备一次一个地加载。

公开(公告)号：US07859314B2

公开(公告)日：2010-12-28

申请号：US12294982

申请日：2007-03-31

申请人： Joseph Rutkowski ,  Alma Anderson

发明人： Joseph Rutkowski ,  Alma Anderson

IPC分类号： H03B1/00

CPC分类号： H03K19/00361 ,  H03K17/166

摘要： Edge-rate control circuits and methods are implemented using a variety of arrangements and methods. Using one such method, an output signal of a bus is controlled by decoupling a feedback capacitor (116) from a gate of a transistor (108) using an isolation switch (106). The transistor (108) is used to control the output signal. A predetermined amount of charge is removed from the feedback capacitor (116) using a charge distribution capacitor (114) that is selectively coupled to the feedback capacitor (116) using a switch (112). The switch (112) is enabled in response to the output signal reaching an output voltage and disabled in response to the charge distribution capacitor (114) reaching a reference voltage.

摘要翻译： 使用各种布置和方法实现边缘速率控制电路和方法。 使用一种这样的方法，通过使用隔离开关（106）使反馈电容器（116）与晶体管（108）的栅极去耦合来控制总线的输出信号。 晶体管（108）用于控制输出信号。 使用使用开关（112）选择性地耦合到反馈电容器（116）的电荷分配电容器（114），从反馈电容器（116）去除预定量的电荷。 开关（112）响应于输出信号达到输出电压而被使能，并且响应于电荷分配电容器（114）达到参考电压而被禁用。

公开(公告)号：US20100264970A1

公开(公告)日：2010-10-21

申请号：US12770793

申请日：2010-04-30

申请人： Alma ANDERSON ,  Joseph RUTKOWSKI ,  Dave OEHLER

发明人： Alma ANDERSON ,  Joseph RUTKOWSKI ,  Dave OEHLER

IPC分类号： H03K5/01

CPC分类号： H03K17/166

摘要： Consistent with an example embodiment, an edge-rate control circuit arrangement (300) for an I2C bus application comprises a first circuit stage (10, M1, M3), responsive to a state transition of a received signal. A second circuit stage (310, 25, 20, 35, 45, M4, ESD) is responsive to the state transition of the received signal and includes drive circuitry (M4) that is activated in response to the state transition of the received signal in order to provide an edge-transition signal for an I2C bus, and regulation circuitry (310, R1, R2, M0, M2) adapted to control the drive circuit and regulate a transition rate for the edge-transition signal, the transition rate being greater than a transition rate of the received signal at the first circuit stage and greater than a minimum and less than a maximum transition rate designated for communication on the I2C bus.

摘要翻译： 与示例实施例一致，用于I2C总线应用的边沿速率控制电路装置（300）包括响应于接收信号的状态转换的第一电路级（10，M1，M3）。 第二电路级（310,25,20,35,45,4H，M4，ESD）响应于接收信号的状态转换，并且包括响应于接收信号的状态转变而被激活的驱动电路（M4） 为了为I2C总线提供边沿转换信号，以及调节电路（310，R1，R2，M0，M2），适用于控制驱动电路并调节边沿转换信号的转换速率，转换速率更大 比第一电路级的接收信号的转换速率高大于最小值，小于指定用于在I2C总线上进行通信的最大转换速率。

公开(公告)号：US20100217903A1

公开(公告)日：2010-08-26

申请号：US12769677

申请日：2010-04-29

申请人： Amrita DESHPANDE ,  Alma Anderson ,  Jean-Marc Irazabal ,  Stephen Blozis ,  Paul Boogaards

发明人： Amrita DESHPANDE ,  Alma Anderson ,  Jean-Marc Irazabal ,  Stephen Blozis ,  Paul Boogaards

IPC分类号： G06F13/00

CPC分类号： G06F13/4291

摘要： Consistent with one example embodiment, communications systems (100,300), using a serial data transfer bus having a serial data line (110) and a clock line (120) used to implement a communications protocol, incorporate programmable loading of a logic value into parallel slave device registers (331-338). The communications system includes a slave device (320) having two or more registers, each register having two or more bits, each register configured to load data therein received in accordance with the communications protocol over the data transfer bus in a first configuration, and to load a single logic value into the plurality of bits in a second configuration. A programmable configuration register is configured to be programmed, in accordance with the communications protocol over the data transfer bus, to select two or more of the registers for loading of the single logic value into the two or more of bits of the selected registers in the second configuration.

摘要翻译： 与一个示例实施例一致，使用用于实现通信协议的具有串行数据线（110）和时钟线（120）的串行数据传输总线的通信系统（100,300）将逻辑值的可编程加载并入并行从机 设备寄存器（331-338）。 通信系统包括具有两个或更多个寄存器的从设备（320），每个寄存器具有两个或多个位，每个寄存器被配置为在第一配置中通过数据传输总线加载根据通信协议接收的数据，以及 在第二配置中将单个逻辑值加载到多个比特中。 可编程配置寄存器被配置为根据数据传输总线上的通信协议来编程，以选择两个或更多个用于将单个逻辑值加载到所选择的寄存器的两个或更多个位中的寄存器 第二配置。

公开(公告)号：US07733142B2

公开(公告)日：2010-06-08

申请号：US11816710

申请日：2006-02-24

申请人： Alma Anderson ,  Joseph Rutkowski ,  Dave Oehler

发明人： Alma Anderson ,  Joseph Rutkowski ,  Dave Oehler

IPC分类号： H03K5/12

CPC分类号： H03K17/166

摘要： Consistent with an example embodiment, an edge-rate control circuit arrangement (300) for an I2C bus application comprises a first circuit stage (10, M1, M3), responsive to a state transition of a received signal. A second circuit stage (310, 25, 20, 35, 45, M4, ESD) is responsive to the state transition of the received signal and includes drive circuitry (M4) that is activated in response to the state transition of the received signal in order to provide an edge-transition signal for an I2C bus, and regulation circuitry (310, R1, R2, M0, M2) adapted to control the drive circuit and regulate a transition rate for the edge-transition signal, the transition rate being greater than a transition rate of the received signal at the first circuit stage and greater than a minimum and less than a maximum transition rate designated for communication on the I2C bus.

摘要翻译： 与示例实施例一致，用于I2C总线应用的边沿速率控制电路装置（300）包括响应于接收信号的状态转换的第一电路级（10，M1，M3）。 第二电路级（310,25,20,35,45,4H，M4，ESD）响应于接收信号的状态转换，并且包括响应于接收信号的状态转变而被激活的驱动电路（M4） 为了为I2C总线提供边沿转换信号，以及调节电路（310，R1，R2，M0，M2），适用于控制驱动电路并调节边沿转换信号的转换速率，转换速率更大 比第一电路级的接收信号的转换速率高大于最小值，小于指定用于在I2C总线上进行通信的最大转换速率。

公开(公告)号：US20090096392A1

公开(公告)日：2009-04-16

申请号：US12294001

申请日：2007-03-20

申请人： Manoj Chandran ,  Alma Anderson

发明人： Manoj Chandran ,  Alma Anderson

IPC分类号： H05B37/02

CPC分类号： H05B33/086 ,  H05B33/0818 ,  Y02B20/346

摘要： Methods and apparatus for implementing and operating pulse width modulation based LED dimmer controllers are described. A synchronization protocol is used to allow control information for the dimmer operations to be transferred to the PWM dimmer control clock domain from an external clock domain, such that visual artifacts are prevented when the control information is updated. Control information may be transferred to the LED dimmer controller via an I2C serial bus, and the synchronization protocol waits for an I2C STOP condition before updating control information across clock domain boundaries. The leading and trailing edges of an asserted group dimmer control signal are generated such that the active portion of the group dimmer control signal overlaps the active portion of individual LED pulse width modulated control signals. In this way, the pulse width modulation of the individual LED control signals is not cut off, or reduced in width by the group dimmer signal.

摘要翻译： 描述了实现和操作基于脉宽调制的LED调光控制器的方法和装置。 同步协议用于允许调光器操作的控制信息从外部时钟域传送到PWM调光控制时钟域，使得当更新控制信息时可防止视觉伪像。 控制信息可以通过I2C串行总线传输到LED调光控制器，并且在更新时钟域边界之间的控制信息之前，同步协议等待I2C STOP条件。 生成断言组调光控制信号的前沿和后沿，使得组调光控制信号的有效部分与各个LED脉冲宽度调制控制信号的有效部分重叠。 以这种方式，各个LED控制信号的脉冲宽度调制不被切断，或者通过组调光信号减小宽度。

公开(公告)号：US06362654B1

公开(公告)日：2002-03-26

申请号：US09641179

申请日：2000-08-17

申请人： Alma Anderson ,  Paul Andrews

发明人： Alma Anderson ,  Paul Andrews

IPC分类号： H03K190175

CPC分类号： G06F13/4045 ,  G06F2213/0016

摘要： A repeater employs multiple threshold detectors to distinguish between signals from external devices and signals generated within the repeater. Signals that are sent from the repeater are configured to be between two threshold levels, so that a detector at one threshold level will detect an active signal, but the detector at the other threshold level will not detect an active signal. When an external signal is received on one side (A) of the repeater, it is propagated to the other side (B) of the repeater, and at the same time, the other side (B) of the repeater is configured to only propagate external signals back to the first side (A). In this manner, the internally generated signal from one side (A) is not propagated back to the same side (A), and a latch-up is avoided. In like manner, when an external signal is received at the other side (B), the first side (A) of the repeater is configured to propagate only externally generated signals. If both sides of the repeater are externally driven, the active signal is propagated to both sides of the repeater, thereby emulating the response that would be provided by a wired bus without a repeater. The repeater is particularly well suited for an I2C bus architecture.

摘要翻译： 中继器使用多个阈值检测器来区分来自外部设备的信号和在中继器内产生的信号。 从中继器发送的信号被配置为在两个阈值电平之间，使得在一个阈值电平处的检测器将检测到有效信号，但是在另一阈值电平处的检测器将不会检测到有效信号。 当在中继器的一侧（A）上接收到外部信号时，它被传播到中继器的另一侧（B），同时中继器的另一侧（B）被配置为仅传播 外部信号回到第一侧（A）。 以这种方式，来自一侧（A）的内部产生的信号不会传播回同一侧（A），并且避免了闩锁。 以相似的方式，当在另一侧（B）接收到外部信号时，中继器的第一侧（A）被配置为仅传播外部产生的信号。 如果中继器的两侧被外部驱动，则有源信号传播到中继器的两侧，从而仿真由无线中继器的有线总线提供的响应。 中继器特别适用于I2C总线架构。

公开(公告)号：US07940102B2

公开(公告)日：2011-05-10

申请号：US12770793

申请日：2010-04-30

申请人： Alma Anderson ,  Joseph Rutkowski ,  Dave Oehler

发明人： Alma Anderson ,  Joseph Rutkowski ,  Dave Oehler

IPC分类号： H03K5/12

CPC分类号： H03K17/166

摘要： Consistent with an example embodiment, an edge-rate control circuit arrangement (300) for an I2C bus application comprises a first circuit stage (10, M1, M3), responsive to a state transition of a received signal. A second circuit stage (310, 25, 20, 35, 45, M4, ESD) is responsive to the state transition of the received signal and includes drive circuitry (M4) that is activated in response to the state transition of the received signal in order to provide an edge-transition signal for an I2C bus, and regulation circuitry (310, R1, R2, M0, M2) adapted to control the drive circuit and regulate a transition rate for the edge-transition signal, the transition rate being greater than a transition rate of the received signal at the first circuit stage and greater than a minimum and less than a maximum transition rate designated for communication on the I2C bus.

摘要翻译： 与示例实施例一致，用于I2C总线应用的边沿速率控制电路装置（300）包括响应于接收信号的状态转换的第一电路级（10，M1，M3）。 第二电路级（310,25,20,35,45,4H，M4，ESD）响应于接收信号的状态转换，并且包括响应于接收信号的状态转变而被激活的驱动电路（M4） 为了为I2C总线提供边沿转换信号，以及调节电路（310，R1，R2，M0，M2），适用于控制驱动电路并调节边沿转换信号的转换速率，转换速率更大 比第一电路级的接收信号的转换速率高大于最小值，小于指定用于在I2C总线上进行通信的最大转换速率。

公开(公告)号：US07761637B2

公开(公告)日：2010-07-20

申请号：US11913061

申请日：2006-05-01

申请人： Amrita Deshpande ,  Alma Anderson ,  Jean-Marc Irazabal ,  Stephen Blozis ,  Paul Boogaards

发明人： Amrita Deshpande ,  Alma Anderson ,  Jean-Marc Irazabal ,  Stephen Blozis ,  Paul Boogaards

IPC分类号： G06F13/24

CPC分类号： G06F13/4291

摘要： Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate latched service requests. Methods for one or more slave devices to request service from a master device involve detecting a condition that asserts a request for service signal, at a common node independent from the serial data transfer bus, to a master device of the bus. The request for service is latched it, within the slave, such that the request for service remains asserted regardless of a change in the detected condition. The request for service is de-asserted in response to interrogation of the slave, using the serial data transfer bus, by the master device. Devices may be configured as general purpose Input/Output devices, CODEC arrangements, or other slave devices, and may conform to I2C and/or SMBus serial communication specifications.

摘要翻译： 与一个示例实施例一致，使用具有串行数据线的串行数据传输总线和用于实现通信协议的时钟线的通信系统包括锁存的服务请求。 用于从主设备请求服务的一个或多个从设备的方法涉及检测在与串行数据传输总线独立的公共节点向服务总线的主设备发出对服务信号的请求的条件。 服务请求在从机中被锁存，使得服务请求保持置位，而不管检测到的状况如何变化。 响应于由主设备使用串行数据传输总线询问从设备，服务请求被取消断言。 设备可以配置为通用输入/输出设备，CODEC布置或其他从设备，并且可以符合I2C和/或SMBus串行通信规范。

公开(公告)号：US20090066381A1

公开(公告)日：2009-03-12

申请号：US11816710

申请日：2006-02-24

申请人： Alma Anderson ,  Joseph Rutkowski ,  Dave Oehler

发明人： Alma Anderson ,  Joseph Rutkowski ,  Dave Oehler

IPC分类号： H03K5/01

CPC分类号： H03K17/166

摘要： In an I2C bus, an edge rate control for an output slows the falling edge of a signal. In an example embodiment, there is an edge rate control circuit for use in an I2C bus. The circuit comprises a resistor divider having a first terminal, a divider terminal, and a second terminal. There is a first NMOS transistor having a source, drain, and gate terminal and a first PMOS transistor having a source, drain, and gate terminal; the source terminals of the first NMOS and first PMOS transistors are coupled to one another; the drain terminal of the first PMOS transistor is coupled to the divider terminal of the resistor divider; the gate of the first PMOS transistor is coupled to the second terminal of the resistor divider; and the drain of the first NMOS transistor is coupled to ground.

摘要翻译： 在I2C总线中，输出的边沿速率控制会降低信号的下降沿。 在示例实施例中，存在用于I2C总线的边沿速率控制电路。 该电路包括具有第一端子，分压器端子和第二端子的电阻器分压器。 存在具有源极，漏极和栅极端子的第一NMOS晶体管和具有源极，漏极和栅极端子的第一PMOS晶体管; 第一NMOS和第一PMOS晶体管的源极端子彼此耦合; 第一PMOS晶体管的漏极端子耦合到电阻分压器的除法器端子; 第一PMOS晶体管的栅极耦合到电阻分压器的第二端; 并且第一NMOS晶体管的漏极耦合到地。