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    Semiconductor device and method of manufacturing the same
    1.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US07795678B2

    公开(公告)日：2010-09-14

    申请号：US12137573

    申请日：2008-06-12

    Applicant: Jong-Man Park ,  Satoru Yanada ,  Sang-Yeon Han ,  Jun-Bum Lee ,  Si-Ok Sohn

    Inventor： Jong-Man Park ,  Satoru Yanada ,  Sang-Yeon Han ,  Jun-Bum Lee ,  Si-Ok Sohn

    IPC: H01L29/739

    CPC classification number: H01L21/76232 ,  H01L27/10876 ,  H01L27/10894

    Abstract: A semiconductor device includes a buried isolation pattern between an active pattern on which transistors are formed and a substrate. The active pattern has adjacent sections each extending longitudinally in a first direction. A field isolation pattern is interposed between the adjacent sections of the active pattern. The buried isolation pattern has sections spaced apart from each other in the first direction under each section of the active pattern. Each section of the buried isolation pattern extends from a lower portion of the field isolation pattern in a second direction perpendicular to the first direction. At least one gate structure is disposed on each section of the active pattern, and an impurity region is located adjacent to the gate structure at the upper surface of the active pattern. The impurity region is spaced from the buried isolation pattern in a third direction perpendicular to the first and second directions. The buried isolation pattern offers a control on the body effect caused by a bias applied to the substrate.

    Abstract translation: 半导体器件包括在其上形成晶体管的有源图案和衬底之间的掩埋隔离图案。 有源图案具有各自沿第一方向纵向延伸的相邻部分。 场隔离图案插入在活动图案的相邻部分之间。 埋置隔离图案具有在活动图案的每个部分下沿第一方向彼此间隔开的部分。 掩埋隔离图案的每个部分在垂直于第一方向的第二方向上从场隔离图案的下部延伸。 至少一个栅极结构设置在有源图案的每个部分上，并且杂质区域位于活性图案的上表面处的栅极结构附近。 杂质区域与第一和第二方向垂直的第三方向与掩埋隔离图案间隔开。 掩埋隔离图案提供了由施加到基底的偏压引起的身体效应的控制。

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    2.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20100197103A1

    公开(公告)日：2010-08-05

    申请号：US12696886

    申请日：2010-01-29

    Applicant: Jun-bum Lee ,  Tae-hong Ha ,  Seong-hwee Cheong

    Inventor： Jun-bum Lee ,  Tae-hong Ha ,  Seong-hwee Cheong

    IPC: H01L21/336

    CPC classification number: H01L29/6656 ,  H01L21/823425 ,  H01L27/1052 ,  H01L27/11536 ,  H01L29/6653

    Abstract: A method of fabricating a semiconductor device can include forming gate structures for transistors on a semiconductor substrate in a cell region and in a peripheral circuit region, forming an offset spacer of a first material on the gate structure, performing first ion implantation for source/drain region formation using the gate structures and the offset spacer as an ion implantation mask, forming a material layer of a second material on the semiconductor substrate and the gate structures, forming a material layer of a third material, which has an etch selectivity with respect to the second material, on the material layer made of the second material, etching-back the material layer made of the third material using the material layer made of the second material as an etch stop layer to form a multi-layered spacer comprising the second material and the third material, performing second ion implantation for source/drain region formation using the gate structures and the multi-layered spacer as an ion implantation mask, and removing the material layer of the third material.

    Abstract translation: 制造半导体器件的方法可以包括在单元区域和周边电路区域中的半导体衬底上形成用于晶体管的栅极结构，在栅极结构上形成第一材料的偏移间隔物，进行源极/漏极的第一离子注入 使用栅极结构和偏移间隔物作为离子注入掩模的区域形成，在半导体衬底上形成第二材料的材料层和栅极结构，形成第三材料的材料层，其具有相对于 在由第二材料制成的材料层上的第二材料使用由第二材料制成的材料层作为蚀刻停止层来蚀刻由第三材料制成的材料层，以形成包含第二材料的多层间隔物 和第三材料，使用门结构和多层温泉进行源/漏区形成的第二离子注入 cer作为离子注入掩模，并且去除第三材料的材料层。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20080308863A1

    公开(公告)日：2008-12-18

    申请号：US12137573

    申请日：2008-06-12

    Applicant: Jong-Man PARK ,  Satoru YANADA ,  Sang-Yeon HAN ,  Jun-Bum LEE ,  Si-Ok SOHN

    Inventor： Jong-Man PARK ,  Satoru YANADA ,  Sang-Yeon HAN ,  Jun-Bum LEE ,  Si-Ok SOHN

    IPC: H01L29/739 ,  H01L21/336

    CPC classification number: H01L21/76232 ,  H01L27/10876 ,  H01L27/10894

    Abstract: A semiconductor device includes a buried isolation pattern between an active pattern on which transistors are formed and a substrate. The active pattern has adjacent sections each extending longitudinally in a first direction. A field isolation pattern is interposed between the adjacent sections of the active pattern. The buried isolation pattern has sections spaced apart from each other in the first direction under each section of the active pattern. Each section of the buried isolation pattern extends from a lower portion of the field isolation pattern in a second direction perpendicular to the first direction. At least one gate structure is disposed on each section of the active pattern, and an impurity region is located adjacent to the gate structure at the upper surface of the active pattern. The impurity region is spaced from the buried isolation pattern in a third direction perpendicular to the first and second directions. The buried isolation pattern offers a control on the body effect caused by a bias applied to the substrate.

    Abstract translation: 半导体器件包括在其上形成晶体管的有源图案和衬底之间的掩埋隔离图案。 有源图案具有各自沿第一方向纵向延伸的相邻部分。 场隔离图案插入在活动图案的相邻部分之间。 埋置隔离图案具有在活动图案的每个部分下沿第一方向彼此间隔开的部分。 掩埋隔离图案的每个部分在垂直于第一方向的第二方向上从场隔离图案的下部延伸。 至少一个栅极结构设置在有源图案的每个部分上，并且杂质区域位于活性图案的上表面处的栅极结构附近。 杂质区域与第一和第二方向垂直的第三方向与掩埋隔离图案间隔开。 掩埋隔离图案提供了由施加到基底的偏压引起的身体效应的控制。

    Method of fabricating semiconductor device
    6.
    发明授权
    Method of fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US08043922B2

    公开(公告)日：2011-10-25

    申请号：US12696886

    申请日：2010-01-29

    Applicant: Jun-bum Lee ,  Tae-hong Ha ,  Seong-hwee Cheong

    Inventor： Jun-bum Lee ,  Tae-hong Ha ,  Seong-hwee Cheong

    IPC: H01L21/336

    CPC classification number: H01L29/6656 ,  H01L21/823425 ,  H01L27/1052 ,  H01L27/11536 ,  H01L29/6653

    Abstract: A method of fabricating a semiconductor device, can be provided by forming gate structures for transistors on a semiconductor substrate in a cell region and in a peripheral circuit region. An offset spacer can be formed including a first material on the gate structures. A first ion implantation can be done using the gate structures and the offset spacer as an ion implantation mask to form source/drain regions. A material layer can be formed including a second material on the semiconductor substrate and on the gate structures. A material layer can be formed of a third material, having an etch selectivity with respect to the second material, on the material layer of the second material. An etch-back can be performed the material layer comprising the third material in the cell region and in the peripheral region, to simultaneously expose the source/drains region in the peripheral region and not expose the source/drain regions in the cell region.

    Abstract translation: 可以通过在单元区域和外围电路区域中的半导体衬底上形成用于晶体管的栅极结构来提供制造半导体器件的方法。 可以在栅极结构上形成包括第一材料的偏移间隔物。 可以使用栅极结构和偏移间隔物作为离子注入掩模来进行第一离子注入以形成源极/漏极区域。 可以在半导体衬底上和门结构上形成包括第二材料的材料层。 材料层可以由第二材料的材料层上具有相对于第二材料的蚀刻选择性的第三材料形成。 可以在单元区域和外围区域中执行包括第三材料的材料层的回蚀，以同时暴露外围区域中的源极/漏极区域，并且不暴露电池区域中的源极/漏极区域。

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