公开(公告)号：US09418044B2

公开(公告)日：2016-08-16

申请号：US10733174

申请日：2003-12-11

申请人： Masaaki Oka ,  Akio Ohba ,  Junichi Asano ,  Junichi Naoi ,  Atsushi Kunimatsu ,  Jiro Amemiya

发明人： Masaaki Oka ,  Akio Ohba ,  Junichi Asano ,  Junichi Naoi ,  Atsushi Kunimatsu ,  Jiro Amemiya

IPC分类号： G06F9/50 ,  G06F15/80

CPC分类号： G06F15/8007 ,  A63F2300/20 ,  A63F2300/60 ,  A63F2300/6063 ,  G06F9/50 ,  G06F9/505

摘要： An entertainment device includes a general-purpose signal processor made up of an assembly of component-processors, each of which can operate in parallel under operating environments independent of others component-processors. A management processor controls a cross bar so as to change the operating environments of the respective component-processors in accordance with a demand for signal processing which is given from a CPU, and to change over any one of the component-processors which receives a signal to be processed which is inputted through the cross bar or outputs a processed signal in accordance with the demand for signal processing.

摘要翻译： 娱乐设备包括由组件处理器组成的通用信号处理器，每个组件处理器可以在独立于其他组件处理器的操作环境下并行操作。 管理处理器控制交叉条，以便根据从CPU给出的对信号处理的需求来改变各个组件处理器的操作环境，并且改变接收信号的任何一个组件处理器 被处理，其通过横杆输入或者根据对信号处理的需求输出处理的信号。

公开(公告)号：US20080278513A1

公开(公告)日：2008-11-13

申请号：US11547299

申请日：2004-12-17

申请人： Junichi Naoi

发明人： Junichi Naoi

IPC分类号： G09G5/36

CPC分类号： G06T15/005 ,  G06F9/321 ,  G06F9/3802 ,  G06F9/3851

摘要： Registers 32a-32d hold data for pixels interleaved. An operator 34 reads the pixel data from the registers and processes the pixel data in accordance with a program code. The operator 34 writes the result of the process back to the registers via a cache 38 or writes it in a memory. Program counters PC0-PC3 provided in association with the number of pixels interleaved store the addresses of instructions in a program for the respective pixels. An instruction loader 76 alternately reads from the program counters. An incrementer 74 increments the count of the program counters. The instructions in the program for the pixels are alternately loaded and interleaved on a pixel by pixel basis, before being supplied to the operator 34 and the like.

摘要翻译： 寄存器32 a- 32 d保存被交错的像素的数据。 操作者34从寄存器读取像素数据，并根据程序代码处理像素数据。 操作者34通过高速缓存38将处理的结果写入寄存器，或将其写入存储器。 与交织的像素数相关联地提供的程序计数器PC 0 -PC 3存储针对各个像素的程序中的指令的地址。 指令装载器76从程序计数器交替地读取。 增量器74增加程序计数器的计数。 在被提供给操作器34等之前，像素的程序中的指令在逐个像素的基础上被交替地加载和交织。

公开(公告)号：US07948487B2

公开(公告)日：2011-05-24

申请号：US11741981

申请日：2007-04-30

申请人： Junichi Naoi

发明人： Junichi Naoi

IPC分类号： G06T15/40

CPC分类号： G06T15/405

摘要： A rendering processing apparatus is provided which performs occlusion culling for excluding from rendering targets a hidden object behind another object as seen from a point of view, when given a plurality of objects. An object input unit stores a plurality of objects in an object storing unit. An internal volume generating unit generates an internal volume which is included in a target object. A reduced Z-buffer updating unit updates a reduced Z-buffer based on the internal volume. An external volume generating unit generates an external volume which includes the target object subject to culling test. A culling determination unit consults the reduced Z-buffer and performs a Z culling test on the target object based on the external volume.

摘要翻译： 提供了一种渲染处理装置，当给定多个对象时，执行遮挡剔除以从再现目标排除另一对象后面的隐藏对象。 对象输入单元将多个对象存储在对象存储单元中。 内部卷生成单元生成包含在目标对象中的内部卷。 减速Z缓冲器更新单元基于内部音量更新减少的Z缓冲器。 外部音量生成单元生成包含被剔除测试的目标对象的外部音量。 剔除确定单元参考减速Z缓冲区，并根据外部体积对目标对象执行Z剔除测试。

公开(公告)号：US07812837B2

公开(公告)日：2010-10-12

申请号：US11741945

申请日：2007-04-30

申请人： Junichi Naoi

发明人： Junichi Naoi

IPC分类号： G06T15/40

CPC分类号： G06T15/405

摘要： A rendering processing apparatus is provided which performs occlusion culling for excluding from rendering targets a hidden object behind another object as seen from a point of view, when given a plurality of objects. An object input unit stores a plurality of objects in an object storing unit. An internal volume generating unit generates an internal volume which is included in a target object. A reduced Z-buffer updating unit updates a reduced Z-buffer based on the internal volume. An external volume generating unit generates an external volume which includes the target object subject to culling test. A culling determination unit consults the reduced Z-buffer and performs a Z culling test on the target object based on the external volume.

摘要翻译： 提供了一种渲染处理装置，当给定多个对象时，执行遮挡剔除以从再现目标排除另一对象后面的隐藏对象。 对象输入单元将多个对象存储在对象存储单元中。 内部卷生成单元生成包含在目标对象中的内部卷。 减速Z缓冲器更新单元基于内部音量更新减少的Z缓冲器。 外部音量生成单元生成包含被剔除测试的目标对象的外部音量。 剔除确定单元参考减速Z缓冲区，并根据外部体积对目标对象执行Z剔除测试。

公开(公告)号：US06320580B1

公开(公告)日：2001-11-20

申请号：US09184240

申请日：1998-11-02

申请人： Keisuke Yasui ,  Jun Okubo ,  Seisuke Morioka ,  Junichi Naoi

发明人： Keisuke Yasui ,  Jun Okubo ,  Seisuke Morioka ,  Junichi Naoi

IPC分类号： G06F1500

CPC分类号： G06T15/40

摘要： Disclosed are an image processing apparatus and an image processing method, which can efficiently execute a hidden-surface process, a blending process on translucent polygons and a shading process by a light source all in a rendering process. An image processing method for generating image data for displaying a plurality of polygons comprises: a mask generation step of receiving polygon data including position data of the polygons in the display screen, generating first mask data indicating effective pixel areas of the polygons in a display screen and Z values indicating depths in the display screen for respective effective pixels from the polygon data, generating second mask data having, as an effective pixel area, a pixel area having a Z value in the foreground of a Z value of another processed polygon among the effective pixel areas of the first mask data, executing an exclusion operation to delete the effective pixel area of the generated second mask data from the effective pixel area of generated second mask data of another polygon to thereby generate trans mask data, and performing generation of the trans mask data polygon by polygon; and a rendering step of implementing a rendering process on each of the polygons with respect to the effective pixel area, indicated by trans mask data generated in the mask generation step.

摘要翻译： 公开了一种图像处理装置和图像处理方法，其能够在渲染过程中有效地执行隐藏表面处理，半透明多边形的混合处理和光源的阴影处理。 一种用于生成用于显示多个多边形的图像数据的图像处理方法，包括：掩模生成步骤，接收包括所述显示画面中的所述多边形的位置数据的多边形数据，生成表示所述多边形在显示画面中的有效像素面积的第一掩模数据 Z值表示来自多边形数据的各有效像素的显示画面的深度，生成具有作为有效像素区域的另一处理多边形的Z值前景中的Z值的像素区域的第二掩模数据， 执行排除操作，从另一多边形的生成的第二掩模数据的有效像素区域中删除所生成的第二掩模数据的有效像素区域，从而生成反掩模数据，并执行生成的第一掩模数据的有效像素区域 多边形反掩模数据多边形; 以及渲染步骤，针对由掩模生成步骤中生成的掩模数据指示的有效像素区域，对每个多边形实现渲染处理。

公开(公告)号：US20060139365A1

公开(公告)日：2006-06-29

申请号：US11302534

申请日：2005-12-13

申请人： Junichi Naoi

发明人： Junichi Naoi

IPC分类号： G09G5/00

CPC分类号： G06T15/005 ,  G06T15/50 ,  G06T15/80

摘要： A shader sends a “completely full” signal to a buffer control unit when a head pixel in a first pass input from a DDA arrives at a final stage of a pipeline process. When the head pixel in the first pass arrives at a stage in the middle of the pipeline process, the shader sends an “almost full” signal to the buffer control unit and a primitive generating unit. Upon receiving the “almost full” signal, the primitive generating unit suspends the generation of rendering primitives in the first pass and starts generating rendering primitives in the second pass. Upon receiving the “almost full” signal, the buffer control unit supplies the rendering primitives in the first pass from the setup processing unit to the DDA via a temporary buffer. Upon receiving the “completely full” signal, the buffer control unit switches to a second pass and directly supplies the rendering primitives in the second pass from the setup processing unit to the DDA.

公开(公告)号：US08203569B2

公开(公告)日：2012-06-19

申请号：US11547299

申请日：2004-12-17

申请人： Junichi Naoi

发明人： Junichi Naoi

IPC分类号： G06F13/372

CPC分类号： G06T15/005 ,  G06F9/321 ,  G06F9/3802 ,  G06F9/3851

摘要： Registers 32a-32d hold data for pixels interleaved. An operator 34 reads the pixel data from the registers and processes the pixel data in accordance with a program code. The operator 34 writes the result of the process back to the registers via a cache 38 or writes it in a memory. Program counters PC0-PC3 provided in association with the number of pixels interleaved store the addresses of instructions in a program for the respective pixels. An instruction loader 76 alternately reads from the program counters. An incrementer 74 increments the count of the program counters. The instructions in the program for the pixels are alternately loaded and interleaved on a pixel by pixel basis, before being supplied to the operator 34 and the like.

摘要翻译： 寄存器32a-32d保存被交错的像素的数据。 操作者34从寄存器读取像素数据，并根据程序代码处理像素数据。 操作者34通过高速缓存38将处理的结果写入寄存器，或将其写入存储器。 与交织的像素数相关联地提供的程序计数器PC0-PC3存储针对各个像素的程序中的指令的地址。 指令装载器76从程序计数器交替地读取。 增量器74增加程序计数器的计数。 在被提供给操作器34等之前，像素的程序中的指令在逐个像素的基础上被交替地加载和交织。

公开(公告)号：US07663634B2

公开(公告)日：2010-02-16

申请号：US11384204

申请日：2006-03-17

申请人： Junichi Naoi

发明人： Junichi Naoi

IPC分类号： G06T1/20

CPC分类号： G06T15/005

摘要： A drawing processing apparatus capable of executing a drawing processing program having conditional branches efficiently by multipass rendering. The drawing processing apparatus comprises arithmetic processing parts including an object input part, a primitive generating part, a raster part, a pixelation part, a distribution part, and a shader which constitute pipeline stages. The shader divides the program into and executes the same in a plurality of passes depending on conditional branches. The shader generates enable flags determining whether or not respective pixels satisfy branch conditions. The flag generating part generates bind enable flags which are the enable flags on the pixels bound into the processing granularities of the pipeline stages, and feeds back the same to the respective pipeline stages. The arithmetic processing parts in the individual pipeline stages refer to the bind enable flags and limit the submission of data not targeted for arithmetic processing in the branched passes.

摘要翻译： 一种能够通过多次渲染有效地执行具有条件分支的绘制处理程序的绘制处理装置。 绘图处理装置包括运算处理部分，包括构成流水线阶段的对象输入部分，原始生成部分，光栅部分，像素化部分，分布部分和着色器。 着色器根据条件分支将程序划分为多个遍中并执行相同的程序。 着色器产生确定相应像素是否满足分支条件的使能标志。 标志生成部分生成绑定使能标志，它们是绑定到流水线级的处理粒度的像素上的使能标志，并将其反馈到相应的流水线级。 各个流水线阶段中的算术处理部分是指绑定使能标志，并限制在分支通过中未针对算术处理的数据的提交。

公开(公告)号：US20080313434A1

公开(公告)日：2008-12-18

申请号：US11793640

申请日：2006-07-25

申请人： Junichi Naoi

发明人： Junichi Naoi

IPC分类号： G06F9/302

CPC分类号： G06T15/005 ,  G06F9/526 ,  G06F12/0875 ,  G09G5/001 ,  G09G5/393

摘要： A DDA 34 notifies the coordinates of a rasterized pixel to an exclusive control part 40, acquires a unique identification number associated with the pixel position from the exclusive control part 40, and adds the identification number to pixel data and supplies it to a shader 20. A plurality of shader pipes 22 in the shader 20 perform arithmetic processing for rendering pixels in parallel, and writes the processing results to a frame buffer 50. When performing an arithmetic instruction that requires exclusive control over a pixel, each shader pipe 22 issues a request to lock the pixel by notifying the identification information added to that pixel to the exclusive control part 40. If the lock request is accepted, the shader pipe 22 performs the arithmetic processing on that pixel. If the lock request is rejected, the shader pipe suspends and puts the arithmetic processing on that pixel into a wait state, and executes arithmetic processing on another pixel in the interim.

摘要翻译： DDA34将光栅化像素的坐标通知给排他控制部分40，从排他控制部分40获取与像素位置相关联的唯一标识号，并将识别号添加到像素数据并将其提供给着色器20。 着色器20中的多个着色器管22执行用于并行渲染像素的算术处理，并将处理结果写入帧缓冲器50.当执行需要对像素进行独占控制的算术指令时，每个着色管22发出请求 通过将添加到该像素的识别信息通知给排他控制部分40来锁定像素。如果接受了锁定请求，则着色管22对该像素执行算术处理。 如果锁定请求被拒绝，则着色器管道暂停并将该像素上的算术处理置于等待状态，并对临时的另一像素执行算术处理。

公开(公告)号：US07406075B2

公开(公告)日：2008-07-29

申请号：US10805366

申请日：2004-03-22

申请人： Junichi Naoi ,  Tomohiro Ohto

发明人： Junichi Naoi ,  Tomohiro Ohto

IPC分类号： H04L12/50

CPC分类号： H04L49/101 ,  H04L49/254

摘要： A small cost-effective crossbar switch is provided. A switch circuit is disposed in each of a plurality of nodes which are cascade connected with each other in a plurality of stages. Each switch circuit receives from a node of a previous stage a designated address to specify directly or indirectly the relative position in which a target switch circuit is present, determines whether the designated address represents a specific value “0”. When it is determined that the specific value is represented, each switch circuit allows data output to a node-out line, decrements the received designated address by “1” to generate a new designated address, and supplies this new designated address to a node of the subsequent stage.

摘要翻译： 提供了一种小型具有成本效益的交叉开关。 开关电路设置在多个节点中的彼此级联的多个节点中的每一个中。 每个开关电路从前一级的节点接收指定地址，以直接或间接地指定存在目标开关电路的相对位置，确定指定地址是否表示特定值“0”。 当确定特定值被表示时，每个开关电路允许数据输出到节点输出线，将接收到的指定地址递减“1”以产生新的指定地址，并将该新指定地址提供给 随后的阶段。