公开(公告)号：US4358782A

公开(公告)日：1982-11-09

申请号：US113043

申请日：1980-01-17

Applicant: Kaoru Takasuka ,  Tatsumi Arakawa ,  Fumio Matushita ,  Hidehiko Kobayashi

Inventor： Kaoru Takasuka ,  Tatsumi Arakawa ,  Fumio Matushita ,  Hidehiko Kobayashi

IPC: H01L31/062 ,  H01L31/20 ,  H01L45/00

CPC classification number: H01L31/062 ,  H01L31/202 ,  Y02E10/50 ,  Y02P70/521

Abstract: A novel semiconductor device having an oxide semiconductor layer between an amorphous silicon hydride and a metallic layer has been found to have an excellent collection efficiency for light, particularly, in the range of short wavelengths and a high energy conversion efficiency as compared with the conventional Schottky barrier semiconductor device and the semiconductor device having a MIS structure. Further, it has been found that the present novel semiconductor device has an excellent storage stability for a long period of time.

Abstract translation: 已经发现，在非晶硅氢化物和金属层之间具有氧化物半导体层的新型半导体器件与常规的肖特基相比具有优异的光收集效率，特别是在短波长范围和高能量转换效率 阻挡半导体器件和具有MIS结构的半导体器件。 此外，已经发现，本发明的新型半导体器件长时间具有优异的存储稳定性。

公开(公告)号：US20240103099A1

公开(公告)日：2024-03-28

申请号：US17974556

申请日：2022-10-27

Applicant: KAORU TAKASUKA ,  Kang-Shuo Chang

Inventor： KAORU TAKASUKA ,  Kang-Shuo Chang

IPC: G01R33/07 ,  G01R33/09

CPC classification number: G01R33/07 ,  G01R33/09

Abstract: A magnetic field sensing device is provided. The magnetic field sensing device includes a magnetoresistance sensor, a Hall sensor, and a calculating circuit. The magnetoresistance sensor senses a magnetic field to provide a magnetoresistance sensing value. The Hall sensor senses the magnetic field to provide a Hall sensing value. The calculating circuit provides a weight value according to the magnetoresistance sensing value, generates a first calculating value according to the weight value and the Hall sensing value, and generates a second calculating value according to the weight value and the magnetoresistance sensing value. The calculating circuit calculates on the first calculating value, the second calculating value, and the magnetoresistance sensing value to generate an output signal with an output value. The output value is associated with a strength of the magnetic field.

公开(公告)号：US12025682B2

公开(公告)日：2024-07-02

申请号：US17974556

申请日：2022-10-27

Applicant: Kaoru Takasuka ,  Kang-Shuo Chang

Inventor： Kaoru Takasuka ,  Kang-Shuo Chang

IPC: G01R33/07 ,  G01R33/09

CPC classification number: G01R33/07 ,  G01R33/09

Abstract: A magnetic field sensing device is provided. The magnetic field sensing device includes a magnetoresistance sensor, a Hall sensor, and a calculating circuit. The magnetoresistance sensor senses a magnetic field to provide a magnetoresistance sensing value. The Hall sensor senses the magnetic field to provide a Hall sensing value. The calculating circuit provides a weight value according to the magnetoresistance sensing value, generates a first calculating value according to the weight value and the Hall sensing value, and generates a second calculating value according to the weight value and the magnetoresistance sensing value. The calculating circuit calculates on the first calculating value, the second calculating value, and the magnetoresistance sensing value to generate an output signal with an output value. The output value is associated with a strength of the magnetic field.

公开(公告)号：US4075498A

公开(公告)日：1978-02-21

申请号：US670610

申请日：1976-03-26

Applicant: Kaoru Takasuka ,  Masatatsu Takahashi ,  Sadaji Nishimura

Inventor： Kaoru Takasuka ,  Masatatsu Takahashi ,  Sadaji Nishimura

IPC: D06H3/08 ,  G01N21/89 ,  G01N21/898 ,  G01N21/32

CPC classification number: G01N21/8915

Abstract: Disclosed is a non-woven fabric defect detecting device in which light is applied to a travelling non-woven fabric to optically or electrically scan the non-woven fabric in its widthwise direction and the light from each point on the non-woven fabric is converted into an electric signal. The converted electric signal is classified into a plurality of levels to detect at least a hole and a heavy filling bar. The durations of these detected outputs are counted in the form of clocks and grading of the quality of the non-woven value is achieved based on the count values. The abovesaid converted output is differentiated and the differentiated output above a predetermined level is detected as fold bar.

公开(公告)号：US20250013256A1

公开(公告)日：2025-01-09

申请号：US18361932

申请日：2023-07-31

Applicant: Kang-Shuo Chang ,  KAORU TAKASUKA

Inventor： Kang-Shuo Chang ,  KAORU TAKASUKA

IPC: G05F3/16

Abstract: A reference current generating circuit including a reference voltage generating circuit and a current source circuit is provided. The reference voltage generating circuit generates a first reference voltage according to a first current. The reference voltage generating circuit includes a native transistor device, and the first current flows through the native transistor device. The current source circuit is coupled to the reference voltage generating circuit. The current source circuit generates a reference current according to the first reference voltage. The current source circuit includes a cascode transistor circuit, and the reference current flows through the cascode transistor circuit. The cascode transistor circuit includes a low-voltage transistor device and a high-voltage transistor device coupled in series.

公开(公告)号：US5150324A

公开(公告)日：1992-09-22

申请号：US460077

申请日：1990-02-06

Applicant: Kaoru Takasuka ,  Ken'ichi Takahashi

Inventor： Kaoru Takasuka ,  Ken'ichi Takahashi

IPC: G06F1/00 ,  G06G7/16 ,  G06G7/161 ,  H03G7/00 ,  H03M3/02 ,  H03M3/04

CPC classification number: G06G7/161 ,  H03M3/43 ,  H03M3/454

Abstract: An analog arithmetic circuit for executing multiplications, divisions, compressions, expansions and combinations thereof. The arithmetic circuit is provided with a .DELTA..SIGMA. modulator comprising an A/D converter and a first D/A converter, a second D/A converter for receiving the output from the .DELTA..SIGMA. modulator, and a low-pass filter which receives the output of the second D/A converter and outputs the result of an arithmetic operation. The arithmetic circuit can be fabricated in the form of a MOS LSI because it does not use a precise triangle waveform generator for pulse width modulation.

Abstract translation: PCT No.PCT / JP89 / 00588 Sec。 371日期1990年2月6日 102（e）1990年2月6日PCT PCT 1989年6月9日PCT公布。 出版物WO89 / 12280 PCT 日期：1989年12月14日。一种用于执行乘法，除法，压缩，扩展及其组合的模拟运算电路。 算术电路设有包括A / D转换器和第一D / A转换器的DELTA SIGMA调制器，用于接收DELTA SIGMA调制器的输出的第二D / A转换器和接收输出的低通滤波器 的第二D / A转换器，并输出算术运算的结果。 算术电路可以以MOS LSI的形式制造，因为它不使用用于脉冲宽度调制的精确三角波形发生器。