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1.发明授权Method, system, and computer program product for cross-invalidation handling in a multi-level private cache 失效用于多级私有缓存中的交叉无效处理的方法，系统和计算机程序产品公开(公告)号：US07890700B2
公开(公告)日：2011-02-15
申请号：US12051736
申请日：2008-03-19
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0815
摘要： A method, system, and computer program product for cross-invalidation handling in a multi-level private cache are provided. The system includes a processor. The processor includes a fetch address register logic in communication with a level 1 data cache, a level 1 instruction cache, a level 2 cache, and a higher level cache. The processor also includes a set of cross-invalidate snapshot counter implemented in the fetch address register. Each cross-invalidate snapshot counter tracks an amount of pending higher level cross-invalidations received before new data for the corresponding cache miss is returned from the higher-level cache. The processor also includes logic executing on the fetch address register for handling level 1 data cache misses and interfacing with the level 2 cache. In response to the new data, and upon determining that older cross-invalidations are pending, the new data is prevented from being used by the processor.
摘要翻译： 提供了一种用于在多级私有缓存中进行交叉无效处理的方法，系统和计算机程序产品。 该系统包括一个处理器。 处理器包括与1级数据高速缓存，1级指令高速缓存，2级高速缓存和更高级高速缓存通信的取指地址寄存器逻辑。 该处理器还包括一组在获取地址寄存器中实现的交叉无效快照计数器。 每个交叉无效快照计数器跟踪在从较高级别的缓存返回相应的高速缓存未命中的新数据之前接收到的未决更高级别的交叉无效的量。 该处理器还包括在取出地址寄存器上执行的逻辑，用于处理1级数据高速缓存未命中并与2级缓存进行接口。 响应于新数据，并且在确定旧的交叉无效正在等待时，防止新数据被处理器使用。
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2.发明申请SYSTEM, METHOD AND PROCESSOR FOR ACCESSING DATA AFTER A TRANSLATION LOOKASIDE BUFFER MISS 有权系统，方法和处理器，用于在翻译预览缓冲区错误后访问数据公开(公告)号：US20090216947A1
公开(公告)日：2009-08-27
申请号：US12037267
申请日：2008-02-26
IPC分类号： G06F12/08
CPC分类号： G06F12/1027 , G06F12/0882 , G06F12/1475 , G06F2212/1016 , G06F2212/684
摘要： Data is accessed in a multi-level hierarchical memory system. A request for data is received, including a virtual address for accessing the data. A translation buffer is queried to obtain an absolute address corresponding to the virtual address. Responsive to the translation buffer not containing an absolute address corresponding to the virtual address, the absolute address is obtained from a translation unit. A directory look-up is performed with the absolute address to determine whether a matching absolute address exists in the directory. A fetch request for the requested data is sent to a next level in the multi-level hierarchical memory system. Processing of the fetch request by the next level occurs in parallel with the directory lookup. The requested data is received in the primary cache to make the requested data available to be written to the primary cache.
摘要翻译： 数据在多级分层存储系统中访问。 接收到数据请求，包括访问数据的虚拟地址。 查询翻译缓冲区以获得与虚拟地址对应的绝对地址。 对于不包含与虚拟地址相对应的绝对地址的翻译缓冲器，从平移单元获得绝对地址。 使用绝对地址执行目录查找，以确定目录中是否存在匹配的绝对地址。 对所请求的数据的提取请求被发送到多级分层存储器系统中的下一级。 与目录查找并行执行提取请求下一级的处理。 在主缓存中接收所请求的数据，以使所请求的数据可用于写入主缓存。
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3.发明授权System, method and processor for accessing data after a translation lookaside buffer miss 有权在翻译后备缓冲区丢失之后访问数据的系统，方法和处理器公开(公告)号：US08195881B2
公开(公告)日：2012-06-05
申请号：US12037267
申请日：2008-02-26
IPC分类号： G06F13/00
CPC分类号： G06F12/1027 , G06F12/0882 , G06F12/1475 , G06F2212/1016 , G06F2212/684
摘要： Data is accessed in a multi-level hierarchical memory system. A request for data is received, including a virtual address for accessing the data. A translation buffer is queried to obtain an absolute address corresponding to the virtual address. Responsive to the translation buffer not containing an absolute address corresponding to the virtual address, the absolute address is obtained from a translation unit. A directory look-up is performed with the absolute address to determine whether a matching absolute address exists in the directory. A fetch request for the requested data is sent to a next level in the multi-level hierarchical memory system. Processing of the fetch request by the next level occurs in parallel with the directory lookup. The requested data is received in the primary cache to make the requested data available to be written to the primary cache.
摘要翻译： 数据在多级分层存储系统中访问。 接收到数据请求，包括访问数据的虚拟地址。 查询翻译缓冲区以获得与虚拟地址对应的绝对地址。 对于不包含与虚拟地址相对应的绝对地址的翻译缓冲器，从平移单元获得绝对地址。 使用绝对地址执行目录查找，以确定目录中是否存在匹配的绝对地址。 对所请求的数据的提取请求被发送到多级分层存储器系统中的下一级。 与目录查找并行执行提取请求下一级的处理。 在主缓存中接收所请求的数据，以使所请求的数据可用于写入主缓存。
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4.发明申请METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR CROSS-INVALIDATION HANDLING IN A MULTI-LEVEL PRIVATE CACHE 失效在多层次私有缓存中进行交叉处理的方法，系统和计算机程序产品公开(公告)号：US20090240889A1
公开(公告)日：2009-09-24
申请号：US12051736
申请日：2008-03-19
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0815
摘要： A method, system, and computer program product for cross-invalidation handling in a multi-level private cache are provided. The system includes a processor. The processor includes a fetch address register logic in communication with a level 1 data cache, a level 1 instruction cache, a level 2 cache, and a higher level cache. The processor also includes a set of cross-invalidate snapshot counter implemented in the fetch address register. Each cross-invalidate snapshot counter tracks an amount of pending higher level cross-invalidations received before new data for the corresponding cache miss is returned from the higher-level cache. The processor also includes logic executing on the fetch address register for handling level 1 data cache misses and interfacing with the level 2 cache. In response to the new data, and upon determining that older cross-invalidations are pending, the new data is prevented from being used by the processor.
摘要翻译： 提供了一种用于在多级私有缓存中进行交叉无效处理的方法，系统和计算机程序产品。 该系统包括一个处理器。 处理器包括与1级数据高速缓存，1级指令高速缓存，2级高速缓存和更高级高速缓存通信的取指地址寄存器逻辑。 该处理器还包括一组在获取地址寄存器中实现的交叉无效快照计数器。 每个交叉无效快照计数器跟踪在从较高级别的缓存返回相应的高速缓存未命中的新数据之前接收到的未决更高级别的交叉无效的量。 该处理器还包括在取出地址寄存器上执行的逻辑，用于处理1级数据高速缓存未命中并与2级缓存进行接口。 响应于新数据，并且在确定旧的交叉无效正在等待时，防止新数据被处理器使用。
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