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1.发明申请SYSTEM, METHOD AND PROCESSOR FOR ACCESSING DATA AFTER A TRANSLATION LOOKASIDE BUFFER MISS 有权系统，方法和处理器，用于在翻译预览缓冲区错误后访问数据公开(公告)号：US20090216947A1
公开(公告)日：2009-08-27
申请号：US12037267
申请日：2008-02-26
IPC分类号： G06F12/08
CPC分类号： G06F12/1027 , G06F12/0882 , G06F12/1475 , G06F2212/1016 , G06F2212/684
摘要： Data is accessed in a multi-level hierarchical memory system. A request for data is received, including a virtual address for accessing the data. A translation buffer is queried to obtain an absolute address corresponding to the virtual address. Responsive to the translation buffer not containing an absolute address corresponding to the virtual address, the absolute address is obtained from a translation unit. A directory look-up is performed with the absolute address to determine whether a matching absolute address exists in the directory. A fetch request for the requested data is sent to a next level in the multi-level hierarchical memory system. Processing of the fetch request by the next level occurs in parallel with the directory lookup. The requested data is received in the primary cache to make the requested data available to be written to the primary cache.
摘要翻译： 数据在多级分层存储系统中访问。 接收到数据请求，包括访问数据的虚拟地址。 查询翻译缓冲区以获得与虚拟地址对应的绝对地址。 对于不包含与虚拟地址相对应的绝对地址的翻译缓冲器，从平移单元获得绝对地址。 使用绝对地址执行目录查找，以确定目录中是否存在匹配的绝对地址。 对所请求的数据的提取请求被发送到多级分层存储器系统中的下一级。 与目录查找并行执行提取请求下一级的处理。 在主缓存中接收所请求的数据，以使所请求的数据可用于写入主缓存。
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2.发明授权System, method and processor for accessing data after a translation lookaside buffer miss 有权在翻译后备缓冲区丢失之后访问数据的系统，方法和处理器公开(公告)号：US08195881B2
公开(公告)日：2012-06-05
申请号：US12037267
申请日：2008-02-26
IPC分类号： G06F13/00
CPC分类号： G06F12/1027 , G06F12/0882 , G06F12/1475 , G06F2212/1016 , G06F2212/684
摘要： Data is accessed in a multi-level hierarchical memory system. A request for data is received, including a virtual address for accessing the data. A translation buffer is queried to obtain an absolute address corresponding to the virtual address. Responsive to the translation buffer not containing an absolute address corresponding to the virtual address, the absolute address is obtained from a translation unit. A directory look-up is performed with the absolute address to determine whether a matching absolute address exists in the directory. A fetch request for the requested data is sent to a next level in the multi-level hierarchical memory system. Processing of the fetch request by the next level occurs in parallel with the directory lookup. The requested data is received in the primary cache to make the requested data available to be written to the primary cache.
摘要翻译： 数据在多级分层存储系统中访问。 接收到数据请求，包括访问数据的虚拟地址。 查询翻译缓冲区以获得与虚拟地址对应的绝对地址。 对于不包含与虚拟地址相对应的绝对地址的翻译缓冲器，从平移单元获得绝对地址。 使用绝对地址执行目录查找，以确定目录中是否存在匹配的绝对地址。 对所请求的数据的提取请求被发送到多级分层存储器系统中的下一级。 与目录查找并行执行提取请求下一级的处理。 在主缓存中接收所请求的数据，以使所请求的数据可用于写入主缓存。
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3.发明授权Method, system, and computer program product for cross-invalidation handling in a multi-level private cache 失效用于多级私有缓存中的交叉无效处理的方法，系统和计算机程序产品公开(公告)号：US07890700B2
公开(公告)日：2011-02-15
申请号：US12051736
申请日：2008-03-19
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0815
摘要： A method, system, and computer program product for cross-invalidation handling in a multi-level private cache are provided. The system includes a processor. The processor includes a fetch address register logic in communication with a level 1 data cache, a level 1 instruction cache, a level 2 cache, and a higher level cache. The processor also includes a set of cross-invalidate snapshot counter implemented in the fetch address register. Each cross-invalidate snapshot counter tracks an amount of pending higher level cross-invalidations received before new data for the corresponding cache miss is returned from the higher-level cache. The processor also includes logic executing on the fetch address register for handling level 1 data cache misses and interfacing with the level 2 cache. In response to the new data, and upon determining that older cross-invalidations are pending, the new data is prevented from being used by the processor.
摘要翻译： 提供了一种用于在多级私有缓存中进行交叉无效处理的方法，系统和计算机程序产品。 该系统包括一个处理器。 处理器包括与1级数据高速缓存，1级指令高速缓存，2级高速缓存和更高级高速缓存通信的取指地址寄存器逻辑。 该处理器还包括一组在获取地址寄存器中实现的交叉无效快照计数器。 每个交叉无效快照计数器跟踪在从较高级别的缓存返回相应的高速缓存未命中的新数据之前接收到的未决更高级别的交叉无效的量。 该处理器还包括在取出地址寄存器上执行的逻辑，用于处理1级数据高速缓存未命中并与2级缓存进行接口。 响应于新数据，并且在确定旧的交叉无效正在等待时，防止新数据被处理器使用。
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4.发明申请METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR CROSS-INVALIDATION HANDLING IN A MULTI-LEVEL PRIVATE CACHE 失效在多层次私有缓存中进行交叉处理的方法，系统和计算机程序产品公开(公告)号：US20090240889A1
公开(公告)日：2009-09-24
申请号：US12051736
申请日：2008-03-19
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0815
摘要： A method, system, and computer program product for cross-invalidation handling in a multi-level private cache are provided. The system includes a processor. The processor includes a fetch address register logic in communication with a level 1 data cache, a level 1 instruction cache, a level 2 cache, and a higher level cache. The processor also includes a set of cross-invalidate snapshot counter implemented in the fetch address register. Each cross-invalidate snapshot counter tracks an amount of pending higher level cross-invalidations received before new data for the corresponding cache miss is returned from the higher-level cache. The processor also includes logic executing on the fetch address register for handling level 1 data cache misses and interfacing with the level 2 cache. In response to the new data, and upon determining that older cross-invalidations are pending, the new data is prevented from being used by the processor.
摘要翻译： 提供了一种用于在多级私有缓存中进行交叉无效处理的方法，系统和计算机程序产品。 该系统包括一个处理器。 处理器包括与1级数据高速缓存，1级指令高速缓存，2级高速缓存和更高级高速缓存通信的取指地址寄存器逻辑。 该处理器还包括一组在获取地址寄存器中实现的交叉无效快照计数器。 每个交叉无效快照计数器跟踪在从较高级别的缓存返回相应的高速缓存未命中的新数据之前接收到的未决更高级别的交叉无效的量。 该处理器还包括在取出地址寄存器上执行的逻辑，用于处理1级数据高速缓存未命中并与2级缓存进行接口。 响应于新数据，并且在确定旧的交叉无效正在等待时，防止新数据被处理器使用。
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公开(公告)号：US09164761B2
公开(公告)日：2015-10-20
申请号：US12033351
申请日：2008-02-19
CPC分类号： G06F9/30032 , G06F9/30101 , G06F9/3879
摘要： A pipelined processor including one or more units having storage locations not directly accessible by software instructions. The processor includes a load-store unit (LSU) in direct communication with the one or more units for accessing the storage locations in response to special instructions. The processor also includes a requesting unit for receiving a special instruction from a requestor and a mechanism for performing a method. The method includes broadcasting storage location information from the special instruction to one or more of the units to determine a corresponding unit having the storage location specified by the special instruction. Execution of the special instruction is initiated at the corresponding unit. If the unit executing the special instruction is not the LSU, the data is sent to the LSU. The data is received from the LSU as a result of the execution of the special instruction. The data is provided to the requester.
摘要翻译： 流水线处理器包括一个或多个单元，其具有不能由软件指令直接访问的存储位置。 处理器包括与一个或多个单元直接通信的加载存储单元（LSU），用于响应于特殊指令访问存储位置。 处理器还包括用于从请求者接收特殊指令的请求单元和用于执行方法的机制。 该方法包括将特定指令中的存储位置信息广播到一个或多个单元，以确定具有由特殊指令指定的存储位置的对应单元。 特殊指令的执行在相应的单位启动。 如果执行特殊指令的单元不是LSU，则将数据发送到LSU。 作为执行特殊指令的结果，从LSU接收数据。 数据被提供给请求者。
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公开(公告)号：US08627047B2
公开(公告)日：2014-01-07
申请号：US12031898
申请日：2008-02-15
申请人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , Brian D. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
发明人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , Brian D. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
CPC分类号： G06F12/0855 , G06F9/3826 , G06F9/3834
摘要： A pipelined microprocessor includes circuitry for store forwarding by performing: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one complete block of data; merging store data from the store request with the complete block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated complete block of data into a store data queue; for each load request, where the load request may require at least one updated completed block of data: determining if store forwarding is appropriate for the load request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the load request.
摘要翻译： 流水线微处理器包括用于存储转发的电路，通过执行以下操作：对于每个存储请求以及对高速缓存和存储器之一的写入待处理; 获取至少一个完整数据块的最新值; 将存储请求的存储数据与完整的数据块合并，从而更新数据块并形成新的最新值和更新的完整数据块; 以及将更新的完整数据块缓冲到存储数据队列中; 对于每个加载请求，其中所述加载请求可能需要至少一个更新的完成的数据块：确定在逐块的基础上存储转发是否适合于所述加载请求; 如果存储转发是适当的，则在逐块的基础上从存储数据队列中选择适当的数据块; 并将所选择的数据块转发到加载请求。
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7.发明授权Method, system and computer program product for storing external device result data 失效用于存储外部设备结果数据的方法，系统和计算机程序产品公开(公告)号：US08250336B2
公开(公告)日：2012-08-21
申请号：US12036695
申请日：2008-02-25
IPC分类号： G06F13/00
CPC分类号： G06F12/084 , G06F9/30043 , G06F9/3824 , G06F9/383 , G06F9/3879
摘要： A method, system, and computer program product for storing result data from an external device. The method includes receiving the result data from the external device, the receiving at a system. The result data is stored into a store data buffer. The store data buffer is utilized by the system to contain store data normally generated by the system. A special store instruction is executed to store the result data into a memory on the system. The special store instruction includes a store address. The executing includes performing an address calculation of the store address based on provided instruction information, and updating a memory location at the store address with contents of the store data buffer utilizing a data path utilized by the system to store data normally generated by the system.
摘要翻译： 一种用于从外部设备存储结果数据的方法，系统和计算机程序产品。 该方法包括从外部设备接收结果数据，在系统接收。 结果数据存储到存储数据缓冲区中。 存储数据缓冲器被系统用于包含通常由系统生成的存储数据。 执行特殊存储指令以将结果数据存储到系统中的存储器中。 特殊商店指令包括商店地址。 所述执行包括基于所提供的指示信息执行所述存储地址的地址计算，以及利用所述系统利用的用于存储由所述系统正常生成的数据的数据路径来更新所述存储数据缓冲器的存储位置。
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8.发明申请PROCESSOR, METHOD AND COMPUTER PROGRAM PRODUCT INCLUDING SPECIALIZED STORE QUEUE AND BUFFER DESIGN FOR SILENT STORE IMPLEMENTATION 有权处理器，方法和计算机程序产品，其中包括专门针对存储商店的特殊店铺和缓冲设计，公开(公告)号：US20090210655A1
公开(公告)日：2009-08-20
申请号：US12031998
申请日：2008-02-15
IPC分类号： G06F9/00
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3826
摘要： A processor including an architecture for limiting store operations includes: a data input and a cache input as inputs to data merge logic; a merge buffer for providing an output to an old data buffer, holding a copy of a memory location and two way communication with a new data buffer; compare logic for receiving old data from the old data buffer and new data from the new data buffer and comparing if the old data matches the new data, and if there is a match determining an existence of a silent store; and store data control logic for limiting store operations while the silent store exists. A method and a computer program product are provided.
摘要翻译： 包括用于限制存储操作的架构的处理器包括：作为数据合并逻辑的输入的数据输入和高速缓存输入; 用于向旧数据缓冲器提供输出的合并缓冲器，保持存储器位置的副本和与新数据缓冲器的双向通信; 比较用于从旧数据缓冲器接收旧数据和来自新数据缓冲器的新数据的比较逻辑，并比较旧数据是否与新数据匹配，以及是否存在确定静默存储的存在的匹配; 并存储用于限制存储操作的数据控制逻辑，同时存在无声存储。 提供了一种方法和计算机程序产品。
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9.发明申请MICROPROCESSOR AND METHOD FOR DEFERRED STORE DATA FORWARDING FOR STORE BACKGROUND DATA IN A SYSTEM WITH NO MEMORY MODEL RESTRICTIONS 有权微处理器和方法，用于存储存储数据的存储数据在没有存储器模型限制的系统中的背景数据公开(公告)号：US20090210632A1
公开(公告)日：2009-08-20
申请号：US12031858
申请日：2008-02-15
申请人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , David B. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
发明人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , David B. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F9/30043
摘要： A pipelined processor includes circuitry adapted for store forwarding, including: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one block of data; merging store data from the store request with the block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated block of data into a store data queue; for each additional store request, where the additional store request requires at least one updated block of data: determining if store forwarding is appropriate for the additional store request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the additional store request.
摘要翻译： 流水线处理器包括适于商店转发的电路，包括：对于每个存储请求，以及在对高速缓存和存储器中的一个进行写入待处理的情况下; 获取至少一个数据块的最新值; 将来自存储请求的存储数据与数据块合并，从而更新数据块并形成新的最新值和更新的完整数据块; 以及将更新的数据块缓冲到存储数据队列中; 对于每个额外的存储请求，其中附加存储请求需要至少一个更新的数据块：确定存储转发是否适合逐块的附加存储请求; 如果存储转发是适当的，则在逐块的基础上从存储数据队列中选择适当的数据块; 以及将所选择的数据块转发到附加存储请求。
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10.发明申请SYSTEM AND METHOD FOR AVOIDING DEADLOCKS WHEN PERFORMING STORAGE UPDATES IN A MULTI-PROCESSOR ENVIRONMENT 有权在多处理器环境中执行存储更新时避免死锁的系统和方法公开(公告)号：US20090204763A1
公开(公告)日：2009-08-13
申请号：US12030627
申请日：2008-02-13
IPC分类号： G06F12/00
CPC分类号： G06F12/0828 , G06F9/3824 , G06F9/3834 , G06F9/3867
摘要： A system and method for avoiding deadlocks when performing storage updates in a multi-processor environment. The system includes a processor having a local cache, a store queue having a temporary buffer with capability to reject exclusive cross-interrogates (XI) while an interrogated cache line is owned exclusive and is to be stored, and a mechanism for performing a method. The method includes setting the processor into a slow mode. A current instruction that includes a data store having one or more target lines is received. The current instruction is executed, with the executing including storing results associated with the data store into the temporary buffer. The store queue is prevented from rejecting an exclusive XI corresponding to the target lines of the current instruction. Each target line is acquired with a status of exclusive ownership, and the contents from the temporary buffer are written to each target line after instruction completion.
摘要翻译： 一种用于在多处理器环境中执行存储更新时避免死锁的系统和方法。 该系统包括具有本地高速缓存的处理器，具有临时缓冲器的存储队列，该临时缓冲器具有拒绝排他交叉询问（XI）的能力，同时询问的高速缓存行被独占地存储并被存储，以及用于执行方法的机制。 该方法包括将处理器设置为慢速模式。 接收包括具有一个或多个目标线的数据存储器的当前指令。 执行当前指令，执行包括将与数据存储相关联的结果存储到临时缓冲器中。 防止存储队列拒绝与当前指令的目标行相对应的排他的XI。 每个目标行被采集为具有独占所有权的状态，并且在指令完成之后将来自临时缓冲器的内容写入每个目标行。
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