公开(公告)号：US5032789A

公开(公告)日：1991-07-16

申请号：US367839

申请日：1989-06-19

申请人： Kamran Firooz ,  Vance Harwood ,  Sharon LaTourrette ,  Jay Stepleton ,  Matt Snook

发明人： Kamran Firooz ,  Vance Harwood ,  Sharon LaTourrette ,  Jay Stepleton ,  Matt Snook

IPC分类号： G01R31/28

CPC分类号： G01R31/2806

摘要： The present invention provides a circuit board tester for performing functional and in-circuit tests on one or more circuit boards. The circuit board tester includes a testhead for interfacing with one or more circuit boards and supplying the resources for the testing thereof. The testhead includes a plurality of modules with each module having a defined amount of resources and a processor for use in executing a test plan to test the circuit board. The circuit board tester further includes a high-speed link for coordinating the execution of a test plan by two or more modules when the resources of one module are insufficient to test a particular circuit board. Each module in the testhead can be selectively connected or disconnected from the high-speed link. Consequently, two or more modules can be connected to the high-speed link to test a first circuit board while another module, that is disconnected from the high-speed link, can concurrently test a second circuit board. The circuit board tester also, preferably, includes a controller that determines whether the resources of more than one module are required to test a particular circuit board and generates a test plan accordingly.

摘要翻译： 本发明提供一种用于对一个或多个电路板执行功能和在电路测试的电路板测试器。 电路板测试器包括用于与一个或多个电路板接口并提供用于其测试的资源的测试头。 测试头包括多个模块，每个模块具有限定的资源量，以及用于执行测试计划以测试电路板的处理器。 当一个模块的资源不足以测试特定电路板时，电路板测试器还包括用于协调由两个或更多个模块执行测试计划的高速链路。 测试头中的每个模块都可以选择性地与高速链路连接或断开连接。 因此，两个或多个模块可以连接到高速链路以测试第一电路板，而与高速链路断开的另一模块可以同时测试第二电路板。 电路板测试器还优选地包括控制器，其确定是否需要多于一个模块的资源来测试特定的电路板并相应地生成测试计划。

公开(公告)号：US5590136A

公开(公告)日：1996-12-31

申请号：US378224

申请日：1995-01-25

申请人： Kamran Firooz

发明人： Kamran Firooz

IPC分类号： G01R31/28

CPC分类号： G01R31/2843

摘要： In an automated test equipment system for testing a circuit board containing a plurality of interconnected digital devices, an in-circuit test is created for a device under test based on stimuli used to test devices which drive the device under test. The method includes the steps of determining, from the electrical interconnect data for the devices on the circuit board, which devices have an output driving an input of the device under test; testing each of the driving devices; observing the response of the device under test during testing of the driving devices; and using the test stimuli for the driving devices and the observed response of the device under test as an in-circuit test for the device under test.

摘要翻译： 在用于测试包含多个互连的数字设备的电路板的自动测试设备系统中，基于用于测试驱动被测设备的设备的刺激，为被测设备创建在线测试。 该方法包括以下步骤：从用于电路板上的设备的电互连数据确定哪些设备具有驱动被测设备的输入的输出; 测试每个驱动装置; 观察驱动装置测试期间被测设备的响应; 并将驱动装置的测试刺激和被测器件的观察响应用作被测器件的在线测试。

公开(公告)号：US4799023A

公开(公告)日：1989-01-17

申请号：US753366

申请日：1985-07-05

申请人： Kamran Firooz ,  Vance R. Harwood ,  Robert C. Illick, Jr. ,  David T. Crook

发明人： Kamran Firooz ,  Vance R. Harwood ,  Robert C. Illick, Jr. ,  David T. Crook

IPC分类号： G01R31/319 ,  G01R31/3193 ,  H03K5/1534 ,  H03K5/22 ,  G01R15/12

CPC分类号： G01R31/31926 ,  G01R31/31937 ,  H03K5/1534

摘要： An improved digital testing device is presented which includes the capability to detect and avoid a pair of common sources of measurement error. One source of error occurs when measurements are made within a Setup time before a transition in the signal under test or during a Hold time after such a transition. This device includes the ability to detect when this occurs and to insert a relative delay between the measurements and transitions to eliminate such errors. The device also detects the existence of a 3-state condition of a point of the circuit under test during the period of a measurement and provides an output indication when such occurs.

摘要翻译： 提出了一种改进的数字测试装置，其包括检测和避免一对常见的测量误差源的能力。 在测试信号转换之前的建立时间内或在这种转换之后的保持时间期间进行测量时，会发生错误的一个来源。 该设备包括检测何时发生这种设备并在测量和转换之间插入相对延迟以消除这种错误的能力。 该装置还在测量期间检测是否存在被测电路的3状态条件，并在发生这种情况时提供输出指示。

公开(公告)号：US5066909A

公开(公告)日：1991-11-19

申请号：US472505

申请日：1990-01-30

申请人： Kamran Firooz

发明人： Kamran Firooz

IPC分类号： G01R19/165 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3193

CPC分类号： G01R31/31724 ,  G01R31/28 ,  G01R31/3193

摘要： Disclosed is a test system having an arbitrary waveform generator, a comparator, and a test controller to analyze the arbitrary signal output from a device under test. The output of the device under test is connected to one input of the comparator and the output of the arbitrary waveform generator is connected to the other input of the comparator. The test controller stimulates the device under test, causing it to perform a function, and stimulates the arbitrary waveform generator, causing it to generate a limit envelope signal. The output of the comparator is continuously monitored by the test controller to determine whether the signal output of the device under test exceeds the limit envelope created by the arbitrary waveform generator.