公开(公告)号：US20070174595A1

公开(公告)日：2007-07-26

申请号：US11336938

申请日：2006-01-23

Applicant: Radhika Thekkath ,  Karagada Kishore ,  Vidya Rajagopalan

Inventor： Radhika Thekkath ,  Karagada Kishore ,  Vidya Rajagopalan

IPC: G06F9/44

CPC classification number: G06F9/3004 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/383 ,  G06F9/384

Abstract: A RISC processor having a data mover engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instruction. The read-tie, single write-tie, and dual write-tie instructions are used to associate software accessible register addresses with memory addresses. These associations effect the operation of the data mover engine such that, for the duration of the associations, the data mover engine routes data to and from associated memory addresses and the execution unit of the processor in response to instructions that specify moving data to and from the associated register addresses. The invention reduces the number of instructions and hardware overhead associated with implementing program loops in a RISC processor.

Abstract translation: 具有数据移动器引擎的RISC处理器和将寄存器地址与存储器地址相关联的指令。 在一个实施例中，指令包括读取连接指令，单个写入指令，双重写入指令和解开指令。 读带，单写和双写指令用于将软件可访问寄存器地址与存储器地址相关联。 这些关联影响数据移动器引擎的操作，使得在关联的持续时间内，数据移动器引擎响应于指定移动数据到和从...移动数据的指令，将数据路由到相关联的存储器地址和处理器的执行单元 关联的寄存器地址。 本发明减少了与RISC处理器中实现程序循环相关联的指令数量和硬件开销。

公开(公告)号：US20070101111A1

公开(公告)日：2007-05-03

申请号：US11261655

申请日：2005-10-31

Applicant: Kjeld Svendsen ,  Maria Ukanwa ,  Karagada Kishore

Inventor： Kjeld Svendsen ,  Maria Ukanwa ,  Karagada Kishore

IPC: G06F9/00

CPC classification number: G06F9/3861 ,  G06F9/3844 ,  G06F9/3851 ,  G06F9/3855

Abstract: A processor core and method for managing program counter redirection in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch portion, a back-end instruction execution portion, and pipeline control logic. Operation of the instruction fetch portion is decoupled from operation of the instruction execution portion. Following detection of a control transfer misprediction, operation of the instruction fetch portion is halted and instructions residing in the instruction fetch portion are invalidated. When the instruction associated with the misprediction reaches a selected pipeline stage, instructions residing in the instruction execution portion of the pipeline are invalidated and the flow of instructions from the instruction fetch portion to the instruction execution portion of the processor pipeline is restarted. A mispredict instruction identification checker and instruction identification tags are used to determine if a control transfer instruction is permitted to redirect instruction fetching.

Abstract translation: 用于在乱序处理器管线中管理程序计数器重定向的处理器核心和方法。 在一个实施例中，处理器核心的流水线包括前端指令获取部分，后端指令执行部分和流水线控制逻辑。 指令提取部分的操作与指令执行部分的操作分离。 在检测到控制传输错误预测之后，停止指令获取部分的操作，并且驻留在指令获取部分中的指令无效。 当与错误预测相关联的指令达到所选择的流水线级时，驻留在流水线的指令执行部分中的指令无效，并且重新开始从指令获取部分到处理器流水线的指令执行部分的指令流。 误用指令识别检查器和指令识别标签用于确定控制传输指令是否允许重定向指令读取。

公开(公告)号：US20050021825A1

公开(公告)日：2005-01-27

申请号：US10819980

申请日：2004-04-08

Applicant: Karagada Kishore ,  Chien-Hsien Wu

Inventor： Karagada Kishore ,  Chien-Hsien Wu

IPC: H04L12/18 ,  H04L12/46 ,  G06F15/16

CPC classification number: H04L12/1881 ,  H04L12/1886 ,  H04L12/4641

Abstract: Various methods are provided for distributing datagrams over telecommunications networks. According to many of these methods, datagrams are multicast or broadcast to one or more nodes or Virtual Local Area Networks (VLANs) on the networks. Also provided are systems for distributing datagrams over the networks according to these methods. According to some of these systems, reductions are provided in the amounts of memory used to multicast and/or broadcast datagrams.

Abstract translation: 提供各种方法用于通过电信网络分发数据报。 根据许多这些方法，数据报是组播或广播到网络上的一个或多个节点或虚拟局域网（VLAN）。 还提供了根据这些方法在网络上分发数据报的系统。 根据这些系统中的一些，对用于组播和/或广播数据报的存储器的数量提供了减少量。

公开(公告)号：US20070101110A1

公开(公告)日：2007-05-03

申请号：US11261654

申请日：2005-10-31

Applicant: Karagada Kishore ,  Kjeld Svendsen ,  Vidya Rajagopalan

Inventor： Karagada Kishore ,  Kjeld Svendsen ,  Vidya Rajagopalan

IPC: G06F9/00

CPC classification number: G06F9/3861 ,  G06F9/3017 ,  G06F9/321 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3844 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3859

Abstract: A processor core and method for managing branch misprediction in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch portion, a back-end instruction execution portion, and pipeline control logic. Operation of the instruction fetch portion is decoupled from operation of the instruction execution portion. Following detection of a control transfer misprediction, operation of the instruction fetch portion is halted and instructions residing in the instruction fetch portion are invalidated. When the instruction associated with the misprediction reaches a selected pipeline stage, instructions residing: in the instruction execution portion of the pipeline are invalidated and the flow of instructions from the instruction fetch portion to the instruction execution portion of the processor pipeline is restarted. A mispredict instruction identification checker and instruction identification tags are used to determine if a control transfer instruction is permitted to redirect instruction fetching.

Abstract translation: 用于在乱序处理器管线中管理分​​支错误预测的处理器核心和方法。 在一个实施例中，处理器核心的流水线包括前端指令获取部分，后端指令执行部分和流水线控制逻辑。 指令提取部分的操作与指令执行部分的操作分离。 在检测到控制传输错误预测之后，停止指令获取部分的操作，并且驻留在指令获取部分中的指令无效。 当与错误预测相关联的指令达到所选择的流水线级时，驻留在流水线的指令执行部分中的指令无效，并且重新开始从指令获取部分到处理器流水线的指令执行部分的指令流。 误用指令识别检查器和指令识别标签用于确定控制传输指令是否允许重定向指令读取。

公开(公告)号：US20050078695A1

公开(公告)日：2005-04-14

申请号：US10819979

申请日：2004-04-08

Applicant: Karagada Kishore ,  Chien-Hsien Wu

Inventor： Karagada Kishore ,  Chien-Hsien Wu

IPC: H04L12/56

CPC classification number: H04L47/10 ,  H04L47/266 ,  H04L47/30 ,  H04L47/32

Abstract: A method and a system for allocating memory in a memory buffer that is part of a data distribution device. Generally, the allocation of memory is for the purpose of storing datagrams. The method allocates memory in the buffer based, at least partially, on how ingress ports that are operably connected to the memory buffer have previously used the buffer to store datagrams. The system typically includes one or more detectors that monitor how various ingresses into the data distribution device are using and have used the memory buffer.

Abstract translation: 一种用于在作为数据分发设备的一部分的存储器缓冲器中分配存储器的方法和系统。 通常，存储器的分配是为了存储数据报的目的。 该方法至少部分地基于可操作地连接到存储器缓冲器的入口端口先前使用缓冲器来存储数据报的方式来分配缓冲器中的存储器。 系统通常包括一个或多个检测器，其监测数据分配设备中的各种入口如何使用并且已经使用存储器缓冲器。