公开(公告)号：US20060205169A1

公开(公告)日：2006-09-14

申请号：US11074905

申请日：2005-03-08

申请人： Jong Yoon ,  Shirin Siddiqui ,  Amitava Chatterjee ,  Brian Goodlin ,  Karen Kirmse

发明人： Jong Yoon ,  Shirin Siddiqui ,  Amitava Chatterjee ,  Brian Goodlin ,  Karen Kirmse

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/6653

摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having L-shaped sidewall spacers (430) on opposing sidewalls thereof and placing source/drain implants (310 or 510) into the substrate (110) proximate the gate structure (130). The method for manufacturing the semiconductor device further includes removing at least a portion of a horizontal segment of the L-shaped sidewall spacers (430).

摘要翻译： 本发明提供一种制造半导体器件的方法和集成电路的制造方法。 除了其他步骤之外，用于制造半导体器件的方法包括在衬底（110）上形成栅极结构（130），所述栅极结构（130）在其相对的侧壁上具有L形侧壁间隔物（430），并且将源极/ 漏极植入物（310或510）进入靠近栅极结构（130）的衬底（110）中。 制造半导体器件的方法还包括去除L形侧壁间隔物（430）的水平段的至少一部分。

公开(公告)号：US20050263834A1

公开(公告)日：2005-12-01

申请号：US11177142

申请日：2005-07-07

申请人： Yuanning Chen ,  Antonio Rotondaro ,  Karen Kirmse

发明人： Yuanning Chen ,  Antonio Rotondaro ,  Karen Kirmse

IPC分类号： H01L21/336 ,  H01L29/49

CPC分类号： H01L29/4983 ,  H01L29/6656 ,  H01L29/6659

摘要： The present invention pertains to formation of a transistor in a manner that mitigates parasitic capacitance, thereby facilitating, inter alia, enhanced switching speeds. More particularly, a sidewall spacer formed upon a semiconductor substrate adjacent a conductive gate structure includes a material having a low dielectric constant (low-k) to mitigate parasitic capacitance between the gate structure, the sidewall spacer and a conductive drain formed within the semiconductor substrate. The low-k sidewall spacer is encapsulated within a nitride material which is selective to etchants such that the spacer is not altered during subsequent processing. The spacer thus retains its shape and remains effective to guide dopants into desired locations within the substrate.

摘要翻译： 本发明涉及以减轻寄生电容的方式形成晶体管，从而有助于特别地提高切换速度。 更具体地，形成在与导电栅极结构相邻的半导体衬底上的侧壁间隔物包括具有低介电常数（低k）的材料，以减轻栅极结构，侧壁间隔物和形成在半导体衬底内的导电漏极之间的寄生电容 。 低k侧壁间隔物被封装在对蚀刻剂有选择性的氮化物材料内，使得间隔物在随后的处理期间不改变。 间隔物因此保持其形状并且仍然有效地将掺杂剂引导到衬底内的期望位置。

公开(公告)号：US20050087775A1

公开(公告)日：2005-04-28

申请号：US10692388

申请日：2003-10-23

申请人： Yuanning Chen ,  Antonio Rotondaro ,  Karen Kirmse

发明人： Yuanning Chen ,  Antonio Rotondaro ,  Karen Kirmse

IPC分类号： H01L21/336 ,  H01L29/49 ,  H01L29/80

CPC分类号： H01L29/4983 ,  H01L29/6656 ,  H01L29/6659

摘要： The present invention pertains to formation of a transistor in a manner that mitigates parasitic capacitance, thereby facilitating, inter alia, enhanced switching speeds. More particularly, a sidewall spacer formed upon a semiconductor substrate adjacent a conductive gate structure includes a material having a low dielectric constant (low-k) to mitigate parasitic capacitance between the gate structure, the sidewall spacer and a conductive drain formed within the semiconductor substrate. The low-k sidewall spacer is encapsulated within a nitride material which is selective to etchants such that the spacer is not altered during subsequent processing. The spacer thus retains its shape and remains effective to guide dopants into desired locations within the substrate.