公开(公告)号：US20060115972A1

公开(公告)日：2006-06-01

申请号：US10999271

申请日：2004-11-29

申请人： Antonio Rotondaro ,  Deborah Riley ,  Trace Hurd

发明人： Antonio Rotondaro ,  Deborah Riley ,  Trace Hurd

IPC分类号： H01L21/4763 ,  H01L21/461

CPC分类号： H01L21/28088 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/32137 ,  H01L29/4966 ,  H01L29/6659

摘要： The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).

摘要翻译： 本发明提供了一种图案化金属栅电极的方法和包括其的集成电路的制造方法。 除了其他步骤之外，用于图案化金属栅电极的方法包括在位于衬底（110）上的栅极电介质层（210）上形成金属栅极电极层（220），并且使用 干蚀刻工艺（410）和湿蚀刻工艺（510）的组合。

公开(公告)号：US20050233533A1

公开(公告)日：2005-10-20

申请号：US10826516

申请日：2004-04-16

申请人： Husam Alshareef ,  Mark Visokay ,  Antonio Rotondaro ,  Luigi Colombo

发明人： Husam Alshareef ,  Mark Visokay ,  Antonio Rotondaro ,  Luigi Colombo

IPC分类号： H01L21/28 ,  H01L21/321 ,  H01L21/4763 ,  H01L21/8238

CPC分类号： H01L21/321 ,  H01L21/28079 ,  H01L21/823835 ,  H01L21/823842

摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first transistor (120) has a metal gate electrode (135) having a work function, and a second transistor (160) located over the semiconductor substrate (110) and proximate the first transistor (120), wherein the second transistor (160) has a plasma altered metal gate electrode (175) having a different work function.

摘要翻译： 本发明提供一种半导体器件及其制造方法以及集成电路的制造方法。 半导体器件（100）以及其他可能的元件包括位于半导体衬底（110）上方的第一晶体管（120），其中第一晶体管（120）具有具有功函数的金属栅电极（135） 第二晶体管（160）位于半导体衬底（110）上并且靠近第一晶体管（120），其中第二晶体管（160）具有具有不同功函数的等离子体改变的金属栅电极（175）。

公开(公告)号：US20050136690A1

公开(公告)日：2005-06-23

申请号：US10739617

申请日：2003-12-18

申请人： Luigi Colombo ,  James Chambers ,  Mark Visokay ,  Antonio Rotondaro

发明人： Luigi Colombo ,  James Chambers ,  Mark Visokay ,  Antonio Rotondaro

IPC分类号： C23C16/56 ,  H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L29/51 ,  H01L29/78 ,  H01L21/31 ,  H01L21/8242 ,  H01L21/469

CPC分类号： H01L21/02318 ,  C23C16/56 ,  H01L21/02323 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3143 ,  H01L21/31608 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/318 ,  H01L29/518 ,  H01L29/78

摘要： A method for improving high-κ gate dielectric film (104) properties. The high-κ film (104) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient (106) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient (108) with a low partial pressure of reducer to remove defects and impurities.

摘要翻译： 一种改善高卡门电介质膜（104）性能的方法。 对高卡帕膜（104）进行两步退火处理。 第一退火在具有低分压氧化剂的还原环境（106）中进行，以促进膜弛豫并增加副产物扩散和解吸附。 第二次退火在具有低分压还原剂的氧化环境（108）中进行以除去缺陷和杂质。

公开(公告)号：US20050136580A1

公开(公告)日：2005-06-23

申请号：US10745313

申请日：2003-12-22

申请人： Luigi Colombo ,  James Chambers ,  Mark Visokay ,  Antonio Rotondaro

发明人： Luigi Colombo ,  James Chambers ,  Mark Visokay ,  Antonio Rotondaro

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/78 ,  H01L21/00 ,  H01L21/4763 ,  H01L21/8234

CPC分类号： H01L29/7833 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/51 ,  H01L29/6656 ,  H01L29/6659

摘要： The present invention pertains to forming a transistor in the absence of hydrogen, or in the presence of a significantly reduced amount of hydrogen. In this manner, a high-k material can be utilized to form a gate dielectric layer in the transistor and facilitate device scaling while mitigating defects that can be introduced into the high-k material by the presence of hydrogen and/or hydrogen containing compounds.

摘要翻译： 本发明涉及在不存在氢的情况下形成晶体管，或者在显着减少量的氢的存在下。 以这种方式，可以利用高k材料在晶体管中形成栅极电介质层，并且便于器件缩放，同时减轻可通过存在氢和/或含氢化合物引入高k材料的缺陷。

公开(公告)号：US20070284676A1

公开(公告)日：2007-12-13

申请号：US11745918

申请日：2007-05-08

申请人： Husam Alshareef ,  Mark Visokay ,  Antonio Rotondaro ,  Luigi Colombo

发明人： Husam Alshareef ,  Mark Visokay ,  Antonio Rotondaro ,  Luigi Colombo

IPC分类号： H01L31/00

CPC分类号： H01L21/321 ,  H01L21/28079 ,  H01L21/823835 ,  H01L21/823842

摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first transistor (120) has a metal gate electrode (135) having a work function, and a second transistor (160) located over the semiconductor substrate (110) and proximate the first transistor (120), wherein the second transistor (160) has a plasma altered metal gate electrode (175) having a different work function.

摘要翻译： 本发明提供一种半导体器件及其制造方法以及集成电路的制造方法。 半导体器件（100）以及其他可能的元件包括位于半导体衬底（110）上方的第一晶体管（120），其中第一晶体管（120）具有具有功函数的金属栅电极（135） 第二晶体管（160）位于半导体衬底（110）上并且靠近第一晶体管（120），其中第二晶体管（160）具有具有不同功函数的等离子体改变的金属栅电极（175）。

公开(公告)号：US20070072363A1

公开(公告)日：2007-03-29

申请号：US11549340

申请日：2006-10-13

申请人： Mark Visokay ,  Luigi Colombo ,  James Chambers ,  Antonio Rotondaro ,  Haowen Bu

发明人： Mark Visokay ,  Luigi Colombo ,  James Chambers ,  Antonio Rotondaro ,  Haowen Bu

IPC分类号： H01L21/8242

CPC分类号： H01L21/28185 ,  H01L21/02148 ,  H01L21/02271 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/3162 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L29/517 ,  H01L29/518

摘要： Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate dielectric. The annealing may be performed before and/or after the nitridation to mitigate deposition and/or nitridation defects and to densify the material while mitigating formation of unwanted low dielectric constant oxides at the interface between the gate dielectric and the semiconductor substrate.

公开(公告)号：US20050205948A1

公开(公告)日：2005-09-22

申请号：US11118647

申请日：2005-04-28

申请人： Antonio Rotondaro ,  Luigi Colombo ,  Malcolm Bevan

发明人： Antonio Rotondaro ,  Luigi Colombo ,  Malcolm Bevan

IPC分类号： H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/78 ,  H01L29/76 ,  H01L31/062

CPC分类号： H01L21/823842 ,  H01L21/823857

摘要： CMOS gate dielectric made of high-k metal silicates by passivating a silicon surface with nitrogen compounds prior to high-k dielectric deposition. Optionally, a silicon dioxide monolayer may be preserved at the interface.

公开(公告)号：US20050130438A1

公开(公告)日：2005-06-16

申请号：US10736444

申请日：2003-12-15

申请人： Antonio Rotondaro ,  Luigi Colombo

发明人： Antonio Rotondaro ,  Luigi Colombo

IPC分类号： H01L21/3115 ,  H01L21/314 ,  H01L21/318 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/823864 ,  H01L21/3115 ,  H01L21/3141 ,  H01L21/3143 ,  H01L21/3185

摘要： Fabricating a semiconductor structure includes establishing a non-stoichiometry associated with a dielectric layer, where the degree of non-stoichiometry corresponds to a nitrogen profile of the dielectric layer. Deposition of the dielectric layer outwardly from a substrate is controlled to substantially yield the established non-stoichiometry of the dielectric layer. Nitrogen is incorporated into the dielectric layer to substantially yield the nitrogen profile without nitridation of the interface.

摘要翻译： 制造半导体结构包括建立与电介质层相关的非化学计量，其中非化学计量的程度对应于电介质层的氮分布。 电介质层从衬底向外沉积被控制以基本上产生介电层的已建立的非化学计量。 将氮气结合到电介质层中以基本上产生氮分布，而不会使界面氮化。

公开(公告)号：US20080057739A1

公开(公告)日：2008-03-06

申请号：US11924132

申请日：2007-10-25

申请人： Luigi Colombo ,  James Chambers ,  Mark Visokay ,  Antonio Rotondaro

发明人： Luigi Colombo ,  James Chambers ,  Mark Visokay ,  Antonio Rotondaro

IPC分类号： H01L21/469

CPC分类号： H01L21/02318 ,  C23C16/56 ,  H01L21/02323 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3143 ,  H01L21/31608 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/318 ,  H01L29/518 ,  H01L29/78

摘要： A method for improving high-κ gate dielectric film (104) properties. The high-κ film (104) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient (106) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient (108) with a low partial pressure of reducer to remove defects and impurities.

摘要翻译： 一种改善高卡门电介质膜（104）性能的方法。 对高卡帕膜（104）进行两步退火处理。 第一退火在具有低分压氧化剂的还原环境（106）中进行，以促进膜弛豫并增加副产物扩散和解吸附。 第二次退火在具有低分压还原剂的氧化环境（108）中进行以除去缺陷和杂质。

公开(公告)号：US20080020558A1

公开(公告)日：2008-01-24

申请号：US11861392

申请日：2007-09-26

申请人： Antonio Rotondaro ,  Deborah Riley ,  Trace Hurd

发明人： Antonio Rotondaro ,  Deborah Riley ,  Trace Hurd

IPC分类号： H01L21/3205

CPC分类号： H01L21/28088 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/32137 ,  H01L29/4966 ,  H01L29/6659

摘要： The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).

摘要翻译： 本发明提供了一种图案化金属栅电极的方法和包括其的集成电路的制造方法。 除了其他步骤之外，用于图案化金属栅电极的方法包括在位于衬底（110）上的栅极电介质层（210）上形成金属栅极电极层（220），并且使用 干蚀刻工艺（410）和湿蚀刻工艺（510）的组合。