公开(公告)号：US07132365B2

公开(公告)日：2006-11-07

申请号：US10914928

申请日：2004-08-10

申请人： Sue Ellen Crank ,  Shirin Siddiqui ,  Deborah J. Riley ,  Trace Quentin Hurd ,  Peijun J. Chen

发明人： Sue Ellen Crank ,  Shirin Siddiqui ,  Deborah J. Riley ,  Trace Quentin Hurd ,  Peijun J. Chen

IPC分类号： H01L21/4763

CPC分类号： H01L21/28518 ,  H01L21/76829

摘要： A method of preparing a die comprises treating exposed silicon to form an oxide prior to silicide formation; and depositing metal on the oxide. The metal may comprise titanium, cobalt, nickel, platinum, palladium, tungsten, molybdenum, or combinations thereof on the oxide. The oxide may be less than or equal to about 15 angstroms thick. In various embodiments, treating exposed silicon to form an oxide comprises forming a non-thermal oxide. Treating exposed silicon to form an oxide may also comprise treating the exposed silicon with an oxidizing plasma; alternatively, treating exposed silicon to form an oxide may comprise forming a chemical oxide. In certain other embodiments, treating exposed silicon to form an oxide comprises treating exposed silicon with a solution comprising ammonium hydroxide, hydrogen peroxide, and water; hydrochloric acid, hydrogen peroxide, and water; hydrogen peroxide; ozone; ozonated deionized water; or combinations thereof.

摘要翻译： 制备模具的方法包括在硅化物形成之前处理暴露的硅以形成氧化物; 并在氧化物上沉积金属。 金属可以在氧化物上包含钛，钴，镍，铂，钯，钨，钼或其组合。 氧化物可以小于或等于约15埃厚。 在各种实施方案中，处理暴露的硅以形成氧化物包括形成非热氧化物。 处理暴露的硅以形成氧化物还可以包括用氧化等离子体处理暴露的硅; 或者，处理暴露的硅以形成氧化物可包括形成化学氧化物。 在某些其他实施方案中，处理暴露的硅以形成氧化物包括用包含氢氧化铵，过氧化氢和水的溶液处理暴露的硅; 盐酸，过氧化氢和水; 过氧化氢; 臭氧; 臭氧化去离子水; 或其组合。

公开(公告)号：US20060024872A1

公开(公告)日：2006-02-02

申请号：US10902902

申请日：2004-07-30

申请人： Brian Goodlin ,  Amitava Chatterjee ,  Shirin Siddiqui ,  Jong Yoon

发明人： Brian Goodlin ,  Amitava Chatterjee ,  Shirin Siddiqui ,  Jong Yoon

IPC分类号： H01L21/338 ,  H01L21/337

CPC分类号： H01L29/6656 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a method for manufacturing a semiconductor device and method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing a semiconductor device (100), among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having sidewall spacers (210 or 410) on opposing sidewalls thereof and placing source/drain implants (310, 510) into the substrate (110) proximate the gate structure (130). The method further includes removing at least a portion of the sidewall spacers (210 or 410) and annealing the source/drain implants (310, 510) to form source/drain regions (710) after removing the at least a portion of the sidewall spacers (210 or 410).

公开(公告)号：US20080145991A1

公开(公告)日：2008-06-19

申请号：US11641578

申请日：2006-12-19

申请人： Manoj Mehrotra ,  Karen Hildegard Ralston Kirmse ,  Shirin Siddiqui

发明人： Manoj Mehrotra ,  Karen Hildegard Ralston Kirmse ,  Shirin Siddiqui

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7836 ,  Y10S257/90

摘要： Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain regions in a semiconductor substrate. The wide sidewall spacers are then removed and slim sidewall spacers are formed alongside a gate stack of the transistor. The slim spacers facilitate transferring stress from an overlying pre metal dielectric (PMD) liner to a channel of the transistor, and also facilitate reducing a resistance in the transistor by allowing silicide regions to be formed closer to the channel. This mitigates yield loss by facilitating predictable or otherwise desirable behavior of the transistor.

摘要翻译： 半导体衬垫在晶体管制造中实现。 更具体地，宽侧壁间隔物最初形成并用于将掺杂剂引导到半导体衬底中的源极/漏极区。 然后去除宽的侧壁间隔物，并且在晶体管的栅极堆叠旁边形成细长的侧壁间隔物。 细长间隔件有助于将应力从上覆的预金属电介质（PMD）衬垫传递到晶体管的通道，并且还有助于通过使硅化物区域形成得更靠近沟道来减小晶体管中的电阻。 这通过促进晶体管的可预测或其它期望的行为来缓解产量损失。

公开(公告)号：US07229869B2

公开(公告)日：2007-06-12

申请号：US11074905

申请日：2005-03-08

申请人： Jong Shik Yoon ,  Shirin Siddiqui ,  Amitava Chatterjee ,  Brian E. Goodlin ,  Karen H. R. Kirmse

发明人： Jong Shik Yoon ,  Shirin Siddiqui ,  Amitava Chatterjee ,  Brian E. Goodlin ,  Karen H. R. Kirmse

IPC分类号： H01L21/8234

CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/6653

摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having L-shaped sidewall spacers (430) on opposing sidewalls thereof and placing source/drain implants (310 or 510) into the substrate (110) proximate the gate structure (130). The method for manufacturing the semiconductor device further includes removing at least a portion of a horizontal segment of the L-shaped sidewall spacers (430).

摘要翻译： 本发明提供一种制造半导体器件的方法和集成电路的制造方法。 除了其他步骤之外，用于制造半导体器件的方法包括在衬底（110）上形成栅极结构（130），所述栅极结构（130）在其相对的侧壁上具有L形侧壁间隔物（430），并且将源极/ 漏极植入物（310或510）进入靠近栅极结构（130）的衬底（110）中。 制造半导体器件的方法还包括去除L形侧壁间隔物（430）的水平段的至少一部分。

公开(公告)号：US20060057810A1

公开(公告)日：2006-03-16

申请号：US10939862

申请日：2004-09-13

申请人： Patricia Smith ,  Majid Mansoori ,  Shirin Siddiqui

发明人： Patricia Smith ,  Majid Mansoori ,  Shirin Siddiqui

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/66628

摘要： According to one embodiment of the invention, a surface preparation method for selective and non-selective epitaxial growth includes providing a substrate having a gate region, a source region, and a drain region, etching a first portion of the source region and the drain region, and removing a second portion of the source region and the drain region by a plasma comprising a noble gas and oxygen.

摘要翻译： 根据本发明的一个实施例，用于选择性和非选择性外延生长的表面制备方法包括提供具有栅极区，源极区和漏极区的衬底，蚀刻源极区和漏极区的第一部分 并且通过包含惰性气体和氧气的等离子体去除源极区域和漏极区域的第二部分。

公开(公告)号：US07344951B2

公开(公告)日：2008-03-18

申请号：US10939862

申请日：2004-09-13

申请人： Patricia B. Smith ,  Majid M. Mansoori ,  Shirin Siddiqui

发明人： Patricia B. Smith ,  Majid M. Mansoori ,  Shirin Siddiqui

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/66628

摘要： According to one embodiment of the invention, a surface preparation method for selective and non-selective epitaxial growth includes providing a substrate having a gate region, a source region, and a drain region, etching a first portion of the source region and the drain region, and removing a second portion of the source region and the drain region by a plasma comprising a noble gas and oxygen.

摘要翻译： 根据本发明的一个实施例，用于选择性和非选择性外延生长的表面制备方法包括提供具有栅极区，源极区和漏极区的衬底，蚀刻源极区和漏极区的第一部分 并且通过包含惰性气体和氧气的等离子体去除源极区域和漏极区域的第二部分。

公开(公告)号：US20060205169A1

公开(公告)日：2006-09-14

申请号：US11074905

申请日：2005-03-08

申请人： Jong Yoon ,  Shirin Siddiqui ,  Amitava Chatterjee ,  Brian Goodlin ,  Karen Kirmse

发明人： Jong Yoon ,  Shirin Siddiqui ,  Amitava Chatterjee ,  Brian Goodlin ,  Karen Kirmse

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/6653

摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having L-shaped sidewall spacers (430) on opposing sidewalls thereof and placing source/drain implants (310 or 510) into the substrate (110) proximate the gate structure (130). The method for manufacturing the semiconductor device further includes removing at least a portion of a horizontal segment of the L-shaped sidewall spacers (430).

摘要翻译： 本发明提供一种制造半导体器件的方法和集成电路的制造方法。 除了其他步骤之外，用于制造半导体器件的方法包括在衬底（110）上形成栅极结构（130），所述栅极结构（130）在其相对的侧壁上具有L形侧壁间隔物（430），并且将源极/ 漏极植入物（310或510）进入靠近栅极结构（130）的衬底（110）中。 制造半导体器件的方法还包括去除L形侧壁间隔物（430）的水平段的至少一部分。

公开(公告)号：US20090184348A1

公开(公告)日：2009-07-23

申请号：US12372868

申请日：2009-02-18

申请人： Manoj Mehrotra ,  Karen Hildegard Ralston Kirmse ,  Shirin Siddiqui

发明人： Manoj Mehrotra ,  Karen Hildegard Ralston Kirmse ,  Shirin Siddiqui

IPC分类号： H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7836 ,  Y10S257/90

摘要： Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain regions in a semiconductor substrate. The wide sidewall spacers are then removed and slim sidewall spacers are formed alongside a gate stack of the transistor. The slim spacers facilitate transferring stress from an overlying pre metal dielectric (PMD) liner to a channel of the transistor, and also facilitate reducing a resistance in the transistor by allowing silicide regions to be formed closer to the channel. This mitigates yield loss by facilitating predictable or otherwise desirable behavior of the transistor.

摘要翻译： 半导体衬垫在晶体管制造中实现。 更具体地，宽侧壁间隔物最初形成并用于将掺杂剂引导到半导体衬底中的源极/漏极区。 然后去除宽的侧壁间隔物，并且在晶体管的栅极堆叠旁边形成细长的侧壁间隔物。 细长间隔件有助于将应力从上覆的预金属电介质（PMD）衬垫传递到晶体管的通道，并且还有助于通过使硅化物区域形成得更靠近沟道来减小晶体管中的电阻。 这通过促进晶体管的可预测或其它期望的行为来缓解产量损失。

公开(公告)号：US07510923B2

公开(公告)日：2009-03-31

申请号：US11641578

申请日：2006-12-19

申请人： Manoj Mehrotra ,  Karen Hildegard Ralston Kirmse ,  Shirin Siddiqui

发明人： Manoj Mehrotra ,  Karen Hildegard Ralston Kirmse ,  Shirin Siddiqui

IPC分类号： H01L21/338

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7836 ,  Y10S257/90

摘要： Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain regions in a semiconductor substrate. The wide sidewall spacers are then removed and slim sidewall spacers are formed alongside a gate stack of the transistor. The slim spacers facilitate transferring stress from an overlying pre metal dielectric (PMD) liner to a channel of the transistor, and also facilitate reducing a resistance in the transistor by allowing silicide regions to be formed closer to the channel. This mitigates yield loss by facilitating predictable or otherwise desirable behavior of the transistor.

摘要翻译： 半导体衬垫在晶体管制造中实现。 更具体地，宽侧壁间隔物最初形成并用于将掺杂剂引导到半导体衬底中的源极/漏极区。 然后去除宽的侧壁间隔物，并且在晶体管的栅极堆叠旁边形成细长的侧壁间隔物。 细长间隔件有助于将应力从上覆的预金属电介质（PMD）衬垫传递到晶体管的通道，并且还有助于通过使硅化物区域形成得更靠近沟道来减小晶体管中的电阻。 这通过促进晶体管的可预测或其它期望的行为来缓解产量损失。

公开(公告)号：US07018888B2

公开(公告)日：2006-03-28

申请号：US10902902

申请日：2004-07-30

申请人： Brian E. Goodlin ,  Amitava Chatterjee ,  Shirin Siddiqui ,  Jong S. Yoon

发明人： Brian E. Goodlin ,  Amitava Chatterjee ,  Shirin Siddiqui ,  Jong S. Yoon

IPC分类号： H01L21/8238

CPC分类号： H01L29/6656 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a method for manufacturing a semiconductor device and method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing a semiconductor device (100), among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having sidewall spacers (210 or 410) on opposing sidewalls thereof and placing source/drain implants (310, 510) into the substrate (110) proximate the gate structure (130). The method further includes removing at least a portion of the sidewall spacers (210 or 410) and annealing the source/drain implants (310, 510) to form source/drain regions (710) after removing the at least a portion of the sidewall spacers (210 or 410).

摘要翻译： 本发明提供一种制造半导体器件的方法和用于制造包括该半导体器件的集成电路的方法。 除了其他步骤之外，制造半导体器件（100）的方法包括在衬底（110）上形成栅极结构（130），所述栅极结构（130）在其相对的侧壁上具有侧壁间隔物（210或410） 源极/漏极注入（310,510）到靠近栅极结构（130）的衬底（110）中。 所述方法还包括：移除所述侧壁间隔物（210或410）的至少一部分并且在去除所述侧壁间隔物的所述至少一部分之后对所述源/漏植入物（310,510）进行退火以形成源极/漏极区域（710） （210或410）。