公开(公告)号：US20180182872A1

公开(公告)日：2018-06-28

申请号：US15796701

申请日：2017-10-27

申请人： SixPoint Materials, Inc.

发明人： Tadao Hashimoto ,  Daisuke Ueda

IPC分类号： H01L29/737 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  C30B7/10 ,  C30B25/20 ,  C30B29/40

CPC分类号： H01L29/7371 ,  C30B7/105 ,  C30B25/20 ,  C30B29/406 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02634 ,  H01L21/02639 ,  H01L21/28575 ,  H01L21/30621 ,  H01L21/3065 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/32 ,  H01L29/36 ,  H01L29/42304 ,  H01L29/452 ,  H01L29/66204 ,  H01L29/66219 ,  H01L29/66318 ,  H01L29/66356 ,  H01L29/66462 ,  H01L29/66924 ,  H01L29/7391 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/8083 ,  H01L29/8611

摘要： The present invention discloses an electronic device formed of a group III nitride. In one embodiment, a substrate is fabricated by the ammonothermal method and a drift layer is fabricated by hydride vapor phase epitaxy. After etching a trench, p-type contact pads are made by pulsed laser deposition followed by n-type contact pads by pulsed laser deposition. The bandgap of the p-type contact pad is designed larger than that of the drift layer. Upon forward bias between p-type contact pads (gate) and n-type contact pads (source), holes and electrons are injected into the drift layer from the p-type contact pads and n-type contact pads. Injected electrons drift to the backside of the substrate (drain).

公开(公告)号：US09960159B2

公开(公告)日：2018-05-01

申请号：US15015564

申请日：2016-02-04

申请人： John V. Veliadis

发明人： John V. Veliadis

IPC分类号： H01L27/088 ,  G06F9/44 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/808

CPC分类号： H01L27/088 ,  G06F8/33 ,  G06F8/72 ,  G06F8/75 ,  H01L21/8232 ,  H01L21/823418 ,  H01L21/823487 ,  H01L27/098 ,  H01L29/0619 ,  H01L29/0657 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66045 ,  H01L29/66068 ,  H01L29/66909 ,  H01L29/66924 ,  H01L29/8083

摘要： A monolithic bi-directional device provides bi-directional power flow and bi-directional blocking of high-voltages. The device includes a first transistor having a first drain formed over a first channel layer that overlays a substrate, and a second transistor that includes a second drain formed over a second channel layer that overlays the substrate. The substrate forms a common source for both the first transistor and the second transistor.

公开(公告)号：US20170222047A1

公开(公告)日：2017-08-03

申请号：US15398652

申请日：2017-01-04

申请人： Lawrence Livermore National Security, LLC

发明人： Adam Conway ,  Sara Elizabeth Harrison ,  Rebecca J. Nikolic ,  Qinghui Shao ,  Lars Voss

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/205 ,  H01L29/20

CPC分类号： H01L29/7827 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66924 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/8083

摘要： In one embodiment, a method of forming a vertical transistor includes forming a layer comprising a semiconductor material above a substrate, defining three dimensional (3D) structures in the layer, forming a second region in at least one vertical sidewall of each 3D structure, and forming an isolation region between the 3D structures. In another embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of 3D structures above the substrate, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure.

公开(公告)号：US09508838B2

公开(公告)日：2016-11-29

申请号：US14657949

申请日：2015-03-13

申请人： Avogy, Inc.

发明人： Linda Romano ,  Andrew Edwards ,  Dave P. Bour ,  Isik C. Kizilyalli

IPC分类号： H01L29/66 ,  H01L29/808 ,  H01L29/20 ,  H01L29/45 ,  H01L29/201 ,  H01L29/205 ,  H01L29/10

CPC分类号： H01L29/66916 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/452 ,  H01L29/66924 ,  H01L29/8083

摘要： A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region. The source includes a GaN-layer coupled to an InGaN layer. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.

摘要翻译： 垂直III族氮化物场效应晶体管包括：包含第一III族氮化物材料的漏极，与漏极电耦合的漏极接触点;以及漂移区域，包括耦合到漏极并邻近漏极设置的第二III族氮化物材料 垂直方向 场效应晶体管还包括沟道区，该沟道区包括耦合到漂移区的第三III族氮化物材料，至少部分围绕沟道区的栅极区和电耦合到栅极区的栅极接触。 场效应晶体管还包括耦合到沟道区的源极。 源包括耦合到InGaN层的GaN层。 沟道区域沿着垂直方向设置在漏极和源极之间，使得垂直III族氮化物场效应晶体管的工作期间的电流沿垂直方向。

公开(公告)号：US20160336432A1

公开(公告)日：2016-11-17

申请号：US15221641

申请日：2016-07-28

申请人： United Silicon Carbide, Inc.

发明人： Anup Bhalla ,  Peter Alexandrov

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/808

CPC分类号： H01L29/66909 ,  H01L21/02378 ,  H01L21/02389 ,  H01L21/26586 ,  H01L21/30604 ,  H01L29/1058 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068 ,  H01L29/66924 ,  H01L29/8083 ,  H01L29/8086

摘要： Trench JFETs may be created by etching trenches into the topside of a substrate of a first doping type to form mesas. The substrate is made up of a backside drain layer, a middle drift layer, and topside source layer. The etching goes through the source layer and partly into the drift layer. Gate regions are formed on the sides and bottoms of the trenches using doping of a second type. Vertical channel regions are formed behind the vertical gate segments via angled implantation using a doping of the first kind, providing improved threshold voltage control. Optionally the substrate may include a lightly doped channel layer between the drift and source layers, such that the mesas include a lightly doped channel region that more strongly contrasts with the implanted vertical channel regions.

摘要翻译： 可以通过将沟槽蚀刻到第一掺杂类型的衬底的顶侧中以形成台面来产生沟槽JFET。 衬底由背面漏极层，中间漂移层和顶层源层构成。 蚀刻通过源极层并部分地进入漂移层。 使用第二类型的掺杂在沟槽的侧面和底部形成栅极区域。 通过使用第一种掺杂的角度注入在垂直栅极段之后形成垂直沟道区，提供改进的阈值电压控制。 可选地，衬底可以包括在漂移层和源层之间的轻掺杂沟道层，使得台面包括与注入的垂直沟道区域更强烈对比的轻掺杂沟道区域。

公开(公告)号：US20160268446A1

公开(公告)日：2016-09-15

申请号：US14642936

申请日：2015-03-10

申请人： United Silicon Carbide, Inc.

发明人： Anup Bhalla ,  Peter Alexandrov

IPC分类号： H01L29/808 ,  H01L29/10 ,  H01L29/20 ,  H01L29/66

CPC分类号： H01L29/66909 ,  H01L21/02378 ,  H01L21/02389 ,  H01L21/26586 ,  H01L21/30604 ,  H01L29/1058 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068 ,  H01L29/66924 ,  H01L29/8083 ,  H01L29/8086

摘要： Trench JFETs may be created by etching trenches into the topside of a substrate of a first doping type to form mesas. The substrate is made up of a backside drain layer, a middle drift layer, and topside source layer. The etching goes through the source layer and partly into the drift layer. Gate regions are formed on the sides and bottoms of the trenches using doping of a second type. Vertical channel regions are formed behind the vertical gate segments via angled implantation using a doping of the first kind, providing improved threshold voltage control. Optionally the substrate may include a lightly doped channel layer between the drift and source layers, such that the mesas include a lightly doped channel region that more strongly contrasts with the implanted vertical channel regions.

公开(公告)号：US20160190351A1

公开(公告)日：2016-06-30

申请号：US14886666

申请日：2015-10-19

申请人： Avogy, Inc.

发明人： Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Linda Romano ,  David P. Bour ,  Richard J. Brown ,  Thomas R. Prunty

IPC分类号： H01L29/808 ,  H01L29/20 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/8083 ,  H01L29/1066 ,  H01L29/1095 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/66909 ,  H01L29/66924

摘要： A vertical field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.

摘要翻译： 垂直场效应晶体管包括：包括第一III族氮化物材料的漏极，与漏极电耦合的漏极接触点;以及漂移区域，该漂移区域包括连接到漏极的第二III族氮化物材料，并且沿垂直方向 。 场效应晶体管还包括沟道区，该沟道区包括耦合到漂移区的第三III族氮化物材料，至少部分围绕沟道区的栅极区和电耦合到栅极区的栅极接触。 场效应晶体管还包括耦合到沟道区的源极和电耦合到源极的源极接触。 沟道区域沿着垂直方向设置在漏极和源极之间，使得垂直III族氮化物场效应晶体管的工作期间的电流沿着垂直方向。

公开(公告)号：US09324844B2

公开(公告)日：2016-04-26

申请号：US14604600

申请日：2015-01-23

申请人： Avogy, Inc.

发明人： Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Linda Romano ,  David P. Bour ,  Richard J. Brown ,  Thomas R. Prunty

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L29/74 ,  H01L29/80 ,  H01L29/66 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/808 ,  H01L29/10 ,  H01L29/20

CPC分类号： H01L29/66909 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/66924 ,  H01L29/8083

摘要： A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, a gate region at least partially surrounding the channel region, having a first surface coupled to the drift region and a second surface on a side of the gate region opposing the first surface, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction, and the channel region extends along at least a portion of the second surface of the gate region.

公开(公告)号：US20160056245A1

公开(公告)日：2016-02-25

申请号：US14930628

申请日：2015-11-02

申请人： Panasonic Intellectual Property Management Co., Ltd.

发明人： YUSUKE KINOSHITA ,  SATOSHI TAMURA ,  TETSUZO UEDA

IPC分类号： H01L29/205 ,  H01L29/66 ,  H01L29/808

CPC分类号： H01L29/205 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/66916 ,  H01L29/66924 ,  H01L29/7786 ,  H01L29/8086

摘要： A semiconductor device includes: a channel layer which is made of InpAlqGa1-p-qN (0≦p+q≦1, 0≦p, and 0≦q); a barrier layer which is formed on the channel layer and is made of InrAlsGa1-r-sN (0≦r+s≦1, 0≦r) having a bandgap larger than that of the channel layer; a diffusion suppression layer which is selectively formed on the barrier layer and is made of IntAluGa1-t-uN (0≦t+u≦1, 0≦t, and s>u); a p-type conductive layer which is formed on the diffusion suppression layer and is made of InxAlyGa1-x-yN (0≦x+y≦1, 0≦y) having p-type conductivity; and a gate electrode which is formed on the p-type conductive layer.

摘要翻译： 半导体器件包括：由InpAlqGa1-p-qN（0＆nlE; p + q＆nlE; 1,0＆amp; nlE; p和0＆nlE; q）制成的沟道层; 阻挡层，其形成在沟道层上，并且由InrAlsGa1-r-sN（0＆lt; nlE; r + s＆nlE; 1,0＆amp; nlE; r）制成，其带隙大于沟道层的带隙; 扩散抑制层，其被选择性地形成在阻挡层上并由IntAluGa1-t-uN（0＆lt; nlE; t + u＆nlE; 1,0＆amp; nlE; t和s> u）制成; p型导电层，其形成在扩散抑制层上，由具有p型导电性的In x Al y Ga 1-x-y N（0＆lt; n 1; x + y＆nlE; 1,0＆amp; 以及形成在p型导电层上的栅电极。

公开(公告)号：US20150340476A1

公开(公告)日：2015-11-26

申请号：US14815780

申请日：2015-07-31

申请人： AVOGY, INC.

发明人： Isik C. Kizilyalli ,  Linda Romano ,  David P. Bour

IPC分类号： H01L29/66 ,  H01L29/808 ,  H01L29/78

CPC分类号： H01L29/66924 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/7832 ,  H01L29/8083

摘要： A vertical JFET includes a III-nitride substrate and a III-nitride epitaxial layer of a first conductivity type coupled to the III-nitride substrate. The first III-nitride epitaxial layer has a first dopant concentration. The vertical JFET also includes a III-nitride epitaxial structure coupled to the first III-nitride epitaxial layer. The III-nitride epitaxial structure includes a set of channels of the first conductivity type and having a second dopant concentration, a set of sources of the first conductivity type, having a third dopant concentration greater than the first dopant concentration, and each characterized by a contact surface, and a set of regrown gates interspersed between the set of channels. An upper surface of the set of regrown gates is substantially coplanar with the contact surfaces of the set of sources.

摘要翻译： 垂直JFET包括III族氮化物衬底和与III族氮化物衬底耦合的第一导电类型的III族氮化物外延层。 第一III族氮化物外延层具有第一掺杂剂浓度。 垂直JFET还包括耦合到第一III族氮化物外延层的III族氮化物外延结构。 III族氮化物外延结构包括一组第一导电类型的沟道并且具有第二掺杂剂浓度，第一导电类型的一组源，其具有大于第一掺杂剂浓度的第三掺杂剂浓度，并且各自的特征在于： 接触表面，以及一组重新生长的门，散布在通道组之间。 该组再生栅极的上表面与该组源的接触表面基本共面。