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1.发明授权III-V compound semiconductor device with a surface layer in access regions having charge of polarity opposite to channel charge and method of making the same 有权III-V族化合物半导体器件，其具有与沟道电荷极性相反的电荷的存取区域中的表面层及其制造方法公开(公告)号：US07682912B2
公开(公告)日：2010-03-23
申请号：US11554859
申请日：2006-10-31
IPC分类号： H01L21/336
CPC分类号： H01L29/66924 , H01L29/2003
摘要： A method of forming a III-V compound semiconductor structure (10) comprises providing a III-V compound semiconductor substrate including a semi-insulating substrate (12) having at least one epitaxial layer formed thereon and further having a gate insulator (14) overlying the at least one epitaxial layer. The at least one epitaxial layer formed on the semi-insulating substrate comprises an epi-structure suitable for use in the formation of a channel of a III-V compound semiconductor MOSFET device, wherein the channel (30) having a first polarity. The method further comprises forming a charge layer (22) at a surface of the gate insulator, the charge layer having a second polarity, wherein the second polarity is opposite to the first polarity.
摘要翻译： 一种形成III-V族化合物半导体结构（10）的方法包括：提供一种III-V族化合物半导体衬底，该III-V族化合物半导体衬底包括半导体衬底（12），该半绝缘衬底具有形成在其上的至少一个外延层，并且还具有覆盖 所述至少一个外延层。 形成在半绝缘衬底上的至少一个外延层包括适于用于形成III-V族化合物半导体MOSFET器件的沟道的外延结构，其中，具有第一极性的沟道（30）。 该方法还包括在栅极绝缘体的表面形成电荷层（22），电荷层具有第二极性，其中第二极性与第一极性相反。
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公开(公告)号：US07799647B2
公开(公告)日：2010-09-21
申请号：US11831394
申请日：2007-07-31
IPC分类号： H01L21/336 , H01L31/00
CPC分类号： H01L29/155 , H01L29/66462
摘要： A method of forming a semiconductor structure includes forming a channel layer; forming a superlattice barrier layer overlying the channel layer, and forming a gate dielectric overlying the superlattice barrier layer. The superlattice barrier layer includes alternating first and second layers of barrier material. In addition, the superlattice barrier layer is configured for increasing a transconductance of the semiconductor device by at least a factor of three over a semiconductor device absent such superlattice barrier layer.
摘要翻译： 形成半导体结构的方法包括形成沟道层; 形成覆盖所述沟道层的超晶格势垒层，以及形成覆盖所述超晶格势垒层的栅极电介质。 超晶格势垒层包括交替的第一和第二层屏障材料。 此外，超晶格势垒层被配置为在没有这种超晶格势垒层的半导体器件上将半导体器件的跨导增加至少三分之一。
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公开(公告)号：US20090032802A1
公开(公告)日：2009-02-05
申请号：US11831394
申请日：2007-07-31
IPC分类号： H01L29/15 , H01L21/336
CPC分类号： H01L29/155 , H01L29/66462
摘要： A method of forming a semiconductor structure comprises forming a channel layer; forming a superlattice barrier layer overlying the channel layer, and forming a gate dielectric overlying the superlattice barrier layer. The superlattice barrier layer includes a plurality of alternating first and second layers of barrier material. In addition, the superlattice barrier layer is configured for increasing a transconductance of the semiconductor device by at least a factor of three over a semiconductor device absent such superlattice barrier layer.
摘要翻译： 形成半导体结构的方法包括形成沟道层; 形成覆盖所述沟道层的超晶格势垒层，以及形成覆盖所述超晶格势垒层的栅极电介质。 超晶格阻挡层包括多个交替的第一和第二层屏障材料。 此外，超晶格势垒层被配置为在没有这种超晶格势垒层的半导体器件上将半导体器件的跨导增加至少三分之一。
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4.发明申请公开(公告)号：US20070090405A1
公开(公告)日：2007-04-26
申请号：US11236187
申请日：2005-09-27
IPC分类号： H01L23/58
CPC分类号： H01L29/66462 , H01L21/02178 , H01L21/02222 , H01L21/02362 , H01L21/28264 , H01L21/318 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor structure comprises providing an insulator layer overlying a III-V compound substrate, the insulator layer having a surface charge layer, the surface charge layer having a deleterious performance effect on the underlying layer or layers of the III-V compound substrate. The method further comprises transforming the surface charge layer into a passivated surface layer, wherein the passivated surface layer reduces the deleterious performance effect on the underlying layer or layers.
摘要翻译： 形成半导体结构的方法包括提供覆盖III-V复合衬底的绝缘体层，所述绝缘体层具有表面电荷层，所述表面电荷层对III-V族化合物的下层或多层具有有害的性能作用 基质。 该方法还包括将表面电荷层转化为钝化表面层，其中钝化表面层减少对下层或下层的有害性能影响。
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5.发明申请III-V COMPOUND SEMICONDUCTOR DEVICE WITH A SURFACE LAYER IN ACCESS REGIONS HAVING CHARGE OF POLARITY OPPOSITE TO CHANNEL CHARGE AND METHOD OF MAKING THE SAME 有权具有带有极性对准电荷的通道区域中具有表面层的III-V族化合物半导体器件及其制造方法公开(公告)号：US20080102607A1
公开(公告)日：2008-05-01
申请号：US11554859
申请日：2006-10-31
IPC分类号： H01L21/20
CPC分类号： H01L29/66924 , H01L29/2003
摘要： A method of forming a III-V compound semiconductor structure (10) comprises providing a III-V compound semiconductor substrate including a semi-insulating substrate (12) having at least one epitaxial layer formed thereon and further having a gate insulator (14) overlying the at least one epitaxial layer. The at least one epitaxial layer formed on the semi-insulating substrate comprises an epi-structure suitable for use in the formation of a channel of a III-V compound semiconductor MOSFET device, wherein the channel (30) having a first polarity. The method further comprises forming a charge layer (22) at a surface of the gate insulator, the charge layer having a second polarity, wherein the second polarity is opposite to the first polarity.
摘要翻译： 一种形成III-V族化合物半导体结构（10）的方法包括：提供一种III-V族化合物半导体衬底，该III-V族化合物半导体衬底包括半导体衬底（12），该半绝缘衬底具有形成在其上的至少一个外延层，并且还具有覆盖 所述至少一个外延层。 形成在半绝缘衬底上的至少一个外延层包括适于用于形成III-V族化合物半导体MOSFET器件的沟道的外延结构，其中，具有第一极性的沟道（30）。 该方法还包括在栅极绝缘体的表面形成电荷层（22），电荷层具有第二极性，其中第二极性与第一极性相反。
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公开(公告)号：US20090085073A1
公开(公告)日：2009-04-02
申请号：US11864274
申请日：2007-09-28
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28264 , H01L29/517
摘要： A method of forming a portion (10) of a compound semiconductor MOSFET structure comprises forming a compound semiconductor layer structure (14) and an oxide layer (20) overlying the same. Forming the compound semiconductor structure (14) includes forming at least one channel material (16) and a group-III rich surface termination layer (18) overlying the at least one channel material. Forming the oxide layer (20) includes forming the oxide layer to overlie the group-III rich surface termination layer and comprises one of (a) depositing essentially congruently evaporating oxide of at least one of (a(i)) a ternary oxide and (a(ii)) an oxide more complex than a ternary oxide and (b) depositing oxide molecules, with use of at least one of (b(i)) a ternary oxide and (b(ii)) an oxide more complex than a ternary oxide.
摘要翻译： 形成化合物半导体MOSFET结构的部分（10）的方法包括：形成化合物半导体层结构（14）和覆盖其上的氧化物层（20）。 形成化合物半导体结构（14）包括形成至少一个沟道材料（16）和覆盖至少一个沟道材料的III族富集表面终止层（18）。 形成氧化物层（20）包括形成氧化物层以覆盖III族富集表面终止层，并且包括（a）基本上一致地沉积（a（i））三元氧化物和（ （ii））比三元氧化物更复杂的氧化物和（b）使用（b（i））三元氧化物和（b（ii））中的至少一种沉积氧化物分子，其比 三元氧化物。
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7.发明申请公开(公告)号：US20060030098A1
公开(公告)日：2006-02-09
申请号：US11239749
申请日：2005-09-30
IPC分类号： H01L21/8238
CPC分类号： H01L21/02266 , H01L21/02175 , H01L21/022 , H01L21/28264 , H01L21/31604 , H01L29/20 , H01L29/513 , H01L29/78
摘要： A method of forming a dielectric layer structure on a supporting semiconductor structure having a first surface comprises providing a first beam of oxide; depositing a first layer of oxide on the first surface of the supporting semiconductor structure using the first beam of oxide, wherein the first layer of oxide has a second surface; terminating the first beam of oxide, and concurrently providing a second beam of oxide, a beam of metal and a beam of oxygen, wherein the first and second beams of oxide are separate and distinct beams of oxide; and depositing a second layer of oxide on the second surface simultaneously using the second beam of oxide, the beam of metal, and the beam of oxygen.
摘要翻译： 在具有第一表面的支撑半导体结构上形成电介质层结构的方法包括：提供第一氧化物束; 使用第一氧化物束在支撑半导体结构的第一表面上沉积第一层氧化物，其中所述第一氧化物层具有第二表面; 终止第一氧化物束，并且同时提供第二氧化物束，金属梁和氧束，其中所述第一和第二氧化物束是分离的和不同的氧化物束; 以及使用所述第二氧化物束，所述金属束和所述氧束将所述第二表面的氧化物沉积在所述第二表面上。
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公开(公告)号：US6159834A
公开(公告)日：2000-12-12
申请号：US22595
申请日：1998-02-12
申请人： Zhiyi (Jimmy) Yu , Matthias Passlack , Brian Bowers , Corey Daniel Overgaard , Ravindranath Droopad , Jonathan Kwadwo Abrokwah
发明人： Zhiyi (Jimmy) Yu , Matthias Passlack , Brian Bowers , Corey Daniel Overgaard , Ravindranath Droopad , Jonathan Kwadwo Abrokwah
IPC分类号： H01L21/28 , H01L21/316 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28264 , H01L21/31604 , H01L21/31666
摘要： A gate quality oxide-compound semiconductor structure (10) is formed by the steps of providing a III-V compound semiconductor wafer structure (13) with an atomically ordered and chemically clean semiconductor surface in an ultra high vacuum (UHV) system (20), directing a molecular beam (26) of gallium oxide onto the surface of the wafer structure to initiate the oxide deposition, and providing a second beam (28) of atomic oxygen to form a Ga.sub.2 O.sub.3 layer (14) with low defect density on the surface of the wafer structure. The second beam of atomic oxygen is supplied upon completion of the first 1-2 monolayers of Ga.sub.2 O.sub.3. The molecular beam of gallium oxide is provided by thermal evaporation from a crystalline Ga.sub.2 O.sub.3 or gallate source, and the atomic beam of oxygen is provided by either RF or microwave plasma discharge, thermal dissociation, or a neutral electron stimulated desorption atom source.
摘要翻译： 通过在超高真空（UHV）系统（20）中提供具有原子级和化学清洁的半导体表面的III-V化合物半导体晶片结构（13）的步骤形成栅极质量氧化物 - 化合物半导体结构（10） 将氧化镓的分子束（26）引导到晶片结构的表面上以引发氧化物沉积，以及提供原子氧的第二光束（28）以在表面上形成具有低缺陷密度的Ga 2 O 3层（14） 的晶片结构。 当第一个1-2单层的Ga2O3完成时，第二个原子氧束被提供。 通过从结晶Ga 2 O 3或没食子酸酯源的热蒸发提供氧化镓的分子束，并且氧原子束由RF或微波等离子体放电，热解离或中性电子刺激的解吸原子源提供。
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公开(公告)号：US08847280B2
公开(公告)日：2014-09-30
申请号：US13293910
申请日：2011-11-10
IPC分类号： H01L29/78 , H01L23/31 , H01L29/778 , H01L29/51 , H01L29/207
CPC分类号： H01L29/7783 , H01L23/3192 , H01L29/207 , H01L29/513 , H01L2924/0002 , H01L2924/12044 , H01L2924/13091 , H01L2924/00
摘要： An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
摘要翻译： 通过提供期望地包括III-V半导体的衬底来获得改进的绝缘栅场效应器件，所述衬底在衬底上具有另外的半导体层，其适于在形成在半导体层上的间隔开的源 - 漏电极之间容纳器件的沟道。 在半导体层上形成介电层。 在电介质层上形成密封层并暴露于氧等离子体。 在源 - 漏电极之间的电介质层上形成栅电极。 电介质层优选包含氧化镓和/或钆 - 镓氧化物，氧等离子体优选为电感耦合等离子体。 希望在密封层的上方设置另外的例如氮化硅的密封层。 否则对泄漏和通道薄层电阻有不利影响的表面状态和栅极电介质阱将大大减少。
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公开(公告)号：US08105925B2
公开(公告)日：2012-01-31
申请号：US12182349
申请日：2008-07-30
IPC分类号： H01L21/26
CPC分类号： H01L29/7783 , H01L23/3192 , H01L29/207 , H01L29/513 , H01L2924/0002 , H01L2924/12044 , H01L2924/13091 , H01L2924/00
摘要： An improved insulated gate field effect device (60) is obtained by providing a substrate (20) desirably comprising a III-V semiconductor, having a further semiconductor layer (22) on the substrate (20) adapted to contain the channel (230) of the device (60) between spaced apart source-drain electrodes (421, 422) formed on the semiconductor layer (22). A dielectric layer (24) is formed on the semiconductor layer (22). A sealing layer (28) is formed on the dielectric layer (24) and exposed to an oxygen plasma (36). A gate electrode (482) is formed on the dielectric layer (24) between the source-drain electrodes (421, 422). The dielectric layer (24) preferably comprises gallium-oxide (25) and/or gadolinium-gallium oxide (26, 27), and the oxygen plasma (36) is preferably an inductively coupled plasma. A further sealing layer (44) of, for example, silicon nitride is desirably provided above the sealing layer (28). Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
摘要翻译： 通过提供期望地包括III-V半导体的衬底（20）来获得改进的绝缘栅场效应器件（60），所述衬底（20）在所述衬底（20）上具有另外的半导体层（22），所述半导体层适于容纳所述沟道（230） 所述器件（60）形成在所述半导体层（22）上形成的间隔开的源 - 漏电极（421,422）之间。 在半导体层（22）上形成介电层（24）。 密封层（28）形成在电介质层（24）上并暴露于氧等离子体（36）。 在源漏电极（421,422）之间的电介质层（24）上形成栅电极（482）。 电介质层（24）优选包含氧化镓（25）和/或氧化钆 - 氧化镓（26,27），氧等离子体（36）优选为电感耦合等离子体。 期望地在密封层（28）的上方设置例如氮化硅的另外的密封层（44）。 否则对泄漏和通道薄层电阻有不利影响的表面状态和栅极电介质阱将大大减少。
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