公开(公告)号：US07725623B2

公开(公告)日：2010-05-25

申请号：US11628684

申请日：2006-05-10

申请人： Katsushi Ohtsuka

发明人： Katsushi Ohtsuka

IPC分类号： G06F3/00

CPC分类号： G06F13/1631 ,  G06F13/1642 ,  G06T1/60 ,  G09G5/001 ,  G09G5/395 ,  G09G2360/125 ,  G09G2360/127

摘要： Commands received from an apparatus that does not support virtual channels are assigned to a virtual channel. A command receiver 210 receives, from an external command transmitting entity that does not support virtual channels, a command designating an address. An assignment information storage unit 228 stores an assignment table in which an address space is divided into a plurality of areas and a channel is assigned to each area. A command storage unit 230 contains queues provided for respective channels, wherein each queue stores received commands temporarily. A distribution destination specifying unit 224 specifies a queue corresponding to an address by referring to the assignment table, and an execution unit 222 transfers the received command to the command storage unit 230 that corresponds to the specified queue.

摘要翻译： 从不支持虚拟通道的设备接收的命令被分配给虚拟通道。 命令接收器210从不支持虚拟信道的外部命令发送实体接收指定地址的命令。 分配信息存储单元228存储其中地址空间被划分为多个区域并且将频道分配给每个区域的分配表。 命令存储单元230包含针对相应通道提供的队列，其中每个队列临时存储接收到的命令。 分发目的地指定单元224通过参考分配表来指定对应于地址的队列，并且执行单元222将接收的命令传送到与指定队列相对应的命令存储单元230。

公开(公告)号：US07644214B2

公开(公告)日：2010-01-05

申请号：US11431966

申请日：2006-05-11

申请人： Katsushi Ohtsuka

发明人： Katsushi Ohtsuka

IPC分类号： G06F13/24 ,  G06F13/32

CPC分类号： G06F9/4812

摘要： An even-driven interrupt processing is efficiently carried out in a multiprocessor system. A main control unit 112 executes a main process as a processing for controlling an apparatus in a unified manner. A sub-control unit 116 executes a task assigned by the main control unit 112 during the execution of the main process, as a sub-process. An event detector 162 detects an event occurrence upon which an interrupt task is to be preferentially executed during the execution of the main process. An interrupt notification unit 164 notifies the sub-control unit 116 of interrupt information indicative of an interrupt task in response to the detected event. The sub-control unit 116 notified of the interrupt information executes the interrupt task specified by the interrupt information, as a sub-process.

摘要翻译： 在多处理器系统中有效地执行均匀驱动的中断处理。 主控制单元112执行作为用于统一控制装置的处理的主处理。 子控制单元116在执行主处理期间执行由主控制单元112分配的任务作为子处理。 事件检测器162检测在执行主处理期间优先执行中断任务的事件发生。 中断通知单元164响应于检测到的事件向子控制单元116通知指示中断任务的中断信息。 通知中断信息的子控制单元116执行由中断信息指定的中断任务作为子处理。

公开(公告)号：US20070277000A1

公开(公告)日：2007-11-29

申请号：US11444803

申请日：2006-06-01

申请人： Katsushi Ohtsuka

发明人： Katsushi Ohtsuka

IPC分类号： G06F12/00

CPC分类号： G06F12/1027 ,  G06F12/1036 ,  G06F12/1081 ,  G06F12/126 ,  G06F2212/654

摘要： Methods and apparatus provide a hardware implemented cache refill circuit for managing at least one address translation table cache, the at least one address translation table cache containing data used to translate an external address into a physical address of a processing system; provide a software implemented cache refill function also for managing the at least one address translation table cache; and simultaneously refill the at least one address translation table cache using the hardware implemented cache refill circuit and the software implemented cache refill function.

摘要翻译： 方法和装置提供一种用于管理至少一个地址转换表缓存的硬件实现的高速缓存补充电路，所述至少一个地址转换表缓存包含用于将外部地址转换为处理系统的物理地址的数据; 提供用于管理所述至少一个地址转换表缓存的软件实现的高速缓存再填充功能; 并且同时使用硬件实现的高速缓冲存储器补充电路和软件实现的缓存再填充功能来再填充所述至少一个地址转换表高速缓存。

公开(公告)号：US20080307115A1

公开(公告)日：2008-12-11

申请号：US11628684

申请日：2006-05-10

申请人： Katsushi Ohtsuka

发明人： Katsushi Ohtsuka

IPC分类号： G06F3/00

CPC分类号： G06F13/1631 ,  G06F13/1642 ,  G06T1/60 ,  G09G5/001 ,  G09G5/395 ,  G09G2360/125 ,  G09G2360/127

摘要： Commands transmitted and received among a plurality of processing units are efficiently controlled. A command receiver 210 receives from an external command transmitting entity a command that has assigned a memory address. An address range of memory is divided into a plurality of areas, and an assignment information storage unit 228 stores an assignment table in which a channel is assigned to each area. A command storage unit 230 contains a queue provided in accordance with each channel wherein the each queue stores received commands temporarily. A distribution destination specifying unit 224 specifies an area that corresponds to a memory address by referring to the assignment table, and an execution unit 222 transfers the received command to a command storage unit that corresponds to said area.

摘要翻译： 有效地控制在多个处理单元之间发送和接收的命令。 命令接收器210从外部命令发送实体接收分配有存储器地址的命令。 存储器的地址范围被分成多个区域，分配信息存储单元228存储其中向每个区域分配频道的分配表。 命令存储单元230包含根据每个通道提供的队列，其中每个队列临时存储接收的命令。 分配目的地指定单元224通过参考分配表来指定对应于存储器地址的区域，并且执行单元222将接收的命令传送到对应于所述区域的命令存储单元。

公开(公告)号：US20060265535A1

公开(公告)日：2006-11-23

申请号：US11431966

申请日：2006-05-11

申请人： Katsushi Ohtsuka

发明人： Katsushi Ohtsuka

IPC分类号： G06F13/24

CPC分类号： G06F9/4812

摘要： An even-driven interrupt processing is efficiently carried out in a multiprocessor system. A main control unit 112 executes a main process as a processing for controlling an apparatus in a unified manner. A sub-control unit 116 executes a task assigned by the main control unit 112 during the execution of the main process, as a sub-process. An event detector 162 detects an event occurrence upon which an interrupt task is to be preferentially executed during the execution of the main process. An interrupt notification unit 164 notifies the sub-control unit 116 of interrupt information indicative of an interrupt task in response to the detected event. The sub-control unit 116 notified of the interrupt information executes the interrupt task specified by the interrupt information, as a sub-process.

摘要翻译： 在多处理器系统中有效地执行均匀驱动的中断处理。 主控制单元112执行作为用于统一控制装置的处理的主处理。 子控制单元116在执行主处理期间执行由主控制单元112分配的任务作为子处理。 事件检测器162检测在执行主处理期间优先执行中断任务的事件发生。 中断通知单元164响应于检测到的事件向子控制单元116通知指示中断任务的中断信息。 通知中断信息的子控制单元116执行由中断信息指定的中断任务作为子处理。

公开(公告)号：US20060277437A1

公开(公告)日：2006-12-07

申请号：US11432107

申请日：2006-05-11

申请人： Katsushi Ohtsuka ,  Takeshi Yamazaki

发明人： Katsushi Ohtsuka ,  Takeshi Yamazaki

IPC分类号： G06F11/00

CPC分类号： G06F9/3879 ,  G06T1/20

摘要： The issuance timing of commands received from and transmitted to among a plurality of processing units is controlled efficiently. An execution command storage unit 222 stores execution commands, received from an external command transmitting entity, where a predetermined upper-limit number of execution commands to be stored is set. An execution command issuing unit 230 retrieves the execution commands stored and issues them to a command execution entity. An adjustment command storage unit 224 stores the adjustment command, transmitted from the command transmitting entity, to adjust the issuance order of the execution commands. A storage area for storing the execution commands to be stored in the execution command storage unit 222 and a storage area for storing the adjustment command to be stored in the adjustment command storage unit 224 are separately provided. When the adjustment command is stored, the execution command issuing unit 230 issues an execution command received after the reception of the adjustment command, on the condition that the issuance of execution commands received prior to the reception of the adjustment command has been completed.

摘要翻译： 有效地控制从多个处理单元接收并发送的命令的发布定时。 执行命令存储单元222存储从外部命令发送实体接收的执行命令，其中设置要存储的预定的上限执行命令。 执行命令发布单元230检索存储的执行命令并将其发布到命令执行实体。 调整命令存储单元224存储从命令发送实体发送的调整命令来调整执行命令的发布顺序。 分别设置用于存储要存储在执行命令存储单元222中的执行命令的存储区域和用于存储要存储在调整命令存储单元224中的调整命令的存储区域。 当存储调整命令时，执行命令发布单元230在接收到调整命令之后接收到的执行命令的发出已经完成的情况下，发出接收到调整命令之后接收到的执行命令。

公开(公告)号：US07886112B2

公开(公告)日：2011-02-08

申请号：US11444803

申请日：2006-06-01

申请人： Katsushi Ohtsuka

发明人： Katsushi Ohtsuka

IPC分类号： G06F13/00

CPC分类号： G06F12/1027 ,  G06F12/1036 ,  G06F12/1081 ,  G06F12/126 ,  G06F2212/654

摘要： Methods and apparatus provide a hardware implemented cache refill circuit for managing at least one address translation table cache, the at least one address translation table cache containing data used to translate an external address into a physical address of a processing system; provide a software implemented cache refill function also for managing the at least one address translation table cache; and simultaneously refill the at least one address translation table cache using the hardware implemented cache refill circuit and the software implemented cache refill function.

摘要翻译： 方法和装置提供一种用于管理至少一个地址转换表缓存的硬件实现的高速缓存补充电路，所述至少一个地址转换表缓存包含用于将外部地址转换为处理系统的物理地址的数据; 提供用于管理所述至少一个地址转换表缓存的软件实现的高速缓存再填充功能; 并且同时使用硬件实现的高速缓冲存储器补充电路和软件实现的缓存再填充功能来再填充所述至少一个地址转换表高速缓存。

公开(公告)号：US07664922B2

公开(公告)日：2010-02-16

申请号：US11431965

申请日：2006-05-11

申请人： Katsushi Ohtsuka ,  Nobuo Sasaki

发明人： Katsushi Ohtsuka ,  Nobuo Sasaki

IPC分类号： G06F12/00

CPC分类号： G06F13/1647

摘要： When a concentration of access requests on a specific bank occurs, the delay time is caused due to the competition among the accesses, thereby lowering the processing speed of an information processing apparatus as a whole. A data transfer arbitration unit 172 sequentially transfers data to be recorded to a memory controller 160 that records data in memory having a plurality of banks. A selector 174 selects any DMAC 170 from among a plurality of DMACs, irrespective of priority sequence of transfer service for the DMAC. A transmitter 176 transmits, to a control-side transfer unit 114, data requested to be transferred by the selected DMAC 170. The selector 174 selects consecutively the DMAC 170 so that the transfer service for the same DMAC is consecutively executed, and determines the number of consecutive selections so that a transfer across the banks of the DMAC 170 occurs by a plurality of the transfer services.

摘要翻译： 当在特定存储体上存在访问请求的集中时，由于访问之间的竞争引起延迟时间，从而降低了信息处理设备整体的处理速度。 数据传输仲裁单元172将要记录的数据顺序地传送到存储器控制器160，存储器控制器160将数据记录在具有多个存储体的存储器中。 选择器174从多个DMAC中选择任何DMAC 170，而与DMAC的传送服务的优先顺序无关。 发送器176向控制侧传送单元114发送请求由所选择的DMAC 170传送的数据。选择器174连续选择DMAC 170，使得连续执行相同DMAC的传送服务，并确定该号码 的连续选择，使得跨越DMAC 170的存储体的传输由多个传送服务发生。

公开(公告)号：US07461240B2

公开(公告)日：2008-12-02

申请号：US11432107

申请日：2006-05-11

申请人： Katsushi Ohtsuka ,  Takeshi Yamazaki

发明人： Katsushi Ohtsuka ,  Takeshi Yamazaki

IPC分类号： G06F13/28

CPC分类号： G06F9/3879 ,  G06T1/20

摘要： The issuance timing of commands received from and transmitted to among a plurality of processing units is controlled efficiently. An execution command storage unit 222 stores execution commands, received from an external command transmitting entity, where a predetermined upper-limit number of execution commands to be stored is set. An execution command issuing unit 230 retrieves the execution commands stored and issues them to a command execution entity. An adjustment command storage unit 224 stores the adjustment command, transmitted from the command transmitting entity, to adjust the issuance order of the execution commands. A storage area for storing the execution commands to be stored in the execution command storage unit 222 and a storage area for storing the adjustment command to be stored in the adjustment command storage unit 224 are separately provided. When the adjustment command is stored, the execution command issuing unit 230 issues an execution command received after the reception of the adjustment command, on the condition that the issuance of execution commands received prior to the reception of the adjustment command has been completed.

摘要翻译： 有效地控制从多个处理单元接收并发送的命令的发布定时。 执行命令存储单元222存储从外部命令发送实体接收的执行命令，其中设置要存储的预定的上限执行命令。 执行命令发布单元230检索存储的执行命令并将其发布到命令执行实体。 调整命令存储单元224存储从命令发送实体发送的调整命令来调整执行命令的发布顺序。 分别设置用于存储要存储在执行命令存储单元222中的执行命令的存储区域和用于存储要存储在调整命令存储单元224中的调整命令的存储区域。 当存储调整命令时，执行命令发布单元230在接收到调整命令之后接收到的执行命令的发出已经完成的情况下，发出接收到调整命令之后接收到的执行命令。

公开(公告)号：US20070016732A1

公开(公告)日：2007-01-18

申请号：US11431965

申请日：2006-05-11

申请人： Katsushi Ohtsuka ,  Nobuo Sasaki

发明人： Katsushi Ohtsuka ,  Nobuo Sasaki

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F13/1647

摘要： When a concentration of access requests on a specific bank occurs, the delay time is caused due to the competition among the accesses, thereby lowering the processing speed of an information processing apparatus as a whole. A data transfer arbitration unit 172 sequentially transfers data to be recorded to a memory controller 160 that records data in memory having a plurality of banks. A selector 174 selects any DMAC 170 from among a plurality of DMACs, irrespective of priority sequence of transfer service for the DMAC. A transmitter 176 transmits, to a control-side transfer unit 114, data requested to be transferred by the selected DMAC 170. The selector 174 selects consecutively the DMAC 170 so that the transfer service for the same DMAC is consecutively executed, and determines the number of consecutive selections so that a transfer across the banks of the DMAC 170 occurs by a plurality of the transfer services.

摘要翻译： 当在特定存储体上存在访问请求的集中时，由于访问之间的竞争引起延迟时间，从而降低了信息处理设备整体的处理速度。 数据传输仲裁单元172将要记录的数据顺序地传送到存储器控制器160，存储器控制器160将数据记录在具有多个存储体的存储器中。 选择器174从多个DMAC中选择任何DMAC 170，而与DMAC的传送服务的优先顺序无关。 发送器176向控制侧传送单元114发送请求由所选择的DMAC 170传送的数据。选择器174连续选择DMAC 170，使得连续执行相同DMAC的传送服务，并确定该号码 的连续选择，使得跨越DMAC 170的存储体的传输由多个传送服务发生。