公开(公告)号：US20050206461A1

公开(公告)日：2005-09-22

申请号：US11075882

申请日：2005-03-10

申请人： Katsutoyo Misawa ,  Yasuyuki Ishikawa ,  Akira Suzuki ,  Yoshinori Teshima ,  Hideaki Ishihara

发明人： Katsutoyo Misawa ,  Yasuyuki Ishikawa ,  Akira Suzuki ,  Yoshinori Teshima ,  Hideaki Ishihara

IPC分类号： G06F1/04 ,  G06F1/26 ,  H03B1/00 ,  H03K3/03

CPC分类号： G06F1/04 ,  G06F1/26 ,  H03K3/0315

摘要： Integrated circuit device includes: a wiring; a clock signal output circuit including a ring oscillator; an internal circuit; an internal power supply generation circuit for supplying an electric power to the clock signal output circuit and to the internal circuit on the basis of a power supplied from an external circuit; and a capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the ring oscillator through the wiring connecting between the internal power supply generation circuit and the capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the internal circuit through the wiring connecting to the capacitor connection terminal.

摘要翻译： 集成电路装置包括：布线; 包括环形振荡器的时钟信号输出电路; 内部电路; 内部电源产生电路，用于根据从外部电路提供的电力向时钟信号输出电路和内部电路提供电力; 和电容器连接端子。 内部电源产生电路通过内部电源产生电路和电容器连接端子之间的布线将电力供给环形振荡器。 内部电源产生电路通过连接到电容器连接端子的布线将电力供给内部电路。

公开(公告)号：US20090009211A1

公开(公告)日：2009-01-08

申请号：US12155017

申请日：2008-05-29

申请人： Naoki Ito ,  Hideaki Ishihara ,  Toshihiko Matsuoka ,  Katsutoyo Misawa

发明人： Naoki Ito ,  Hideaki Ishihara ,  Toshihiko Matsuoka ,  Katsutoyo Misawa

IPC分类号： H03K19/00

CPC分类号： G06F11/26

摘要： A microcomputer for functioning according to operation modes includes: a mode counter that counts the number of times of level change in a signal applied to a mode setting terminal; a mode decoder that decodes output data of the mode counter to output a mode signal, which represents one operation mode; a clock input terminal; a data terminal through which serial data is inputted synchronously with a serial clock signal applied to the clock input terminal; a serial-to-parallel conversion unit that converts the serial data into parallel data and stores the parallel data in an input data buffer; and a switching means that switches to a state that a CPU can access to the input data buffer in a test mode. In the test mode, test instruction data is capable of being inputted from an external circuit.

摘要翻译： 根据操作模式起作用的微计算机包括：对施加到模式设置终端的信号中的电平变化次数进行计数的模式计数器; 解码模式计数器的输出数据以输出表示一种操作模式的模式信号的模式解码器; 时钟输入端子; 数据终端，串行数据与施加到时钟输入端的串行时钟信号同步输入; 串行到并行转换单元，将串行数据转换为并行数据，并将并行数据存储在输入数据缓冲器中; 以及切换装置，切换到CPU能够以测试模式访问输入数据缓冲器的状态。 在测试模式下，能够从外部电路输入测试指令数据。

公开(公告)号：US07221206B2

公开(公告)日：2007-05-22

申请号：US11075882

申请日：2005-03-10

申请人： Katsutoyo Misawa ,  Yasuyuki Ishikawa ,  Akira Suzuki ,  Yoshinori Teshima ,  Hideaki Ishihara

发明人： Katsutoyo Misawa ,  Yasuyuki Ishikawa ,  Akira Suzuki ,  Yoshinori Teshima ,  Hideaki Ishihara

IPC分类号： G06F1/04

CPC分类号： G06F1/04 ,  G06F1/26 ,  H03K3/0315

摘要： Integrated circuit device includes: a wiring; a clock signal output circuit including a ring oscillator; an internal circuit; an internal power supply generation circuit for supplying an electric power to the clock signal output circuit and to the internal circuit on the basis of a power supplied from an external circuit; and a capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the ring oscillator through the wiring connecting between the internal power supply generation circuit and the capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the internal circuit through the wiring connecting to the capacitor connection terminal.

摘要翻译： 集成电路装置包括：布线; 包括环形振荡器的时钟信号输出电路; 内部电路; 内部电源产生电路，用于根据从外部电路提供的电力向时钟信号输出电路和内部电路提供电力; 和电容器连接端子。 内部电源产生电路通过内部电源产生电路和电容器连接端子之间的布线将电力供给环形振荡器。 内部电源产生电路通过连接到电容器连接端子的布线将电力供给内部电路。

公开(公告)号：US20050206429A1

公开(公告)日：2005-09-22

申请号：US11073564

申请日：2005-03-08

申请人： Katsutoyo Misawa ,  Yasuyuki Ishikawa ,  Akira Suzuki ,  Yoshinori Teshima ,  Hideaki Ishihara ,  Toshiharu Muramatsu

发明人： Katsutoyo Misawa ,  Yasuyuki Ishikawa ,  Akira Suzuki ,  Yoshinori Teshima ,  Hideaki Ishihara ,  Toshiharu Muramatsu

IPC分类号： H03K5/08 ,  H03L5/00

CPC分类号： H03K5/08

摘要： In a clamp circuit device, reference voltages are set up by a series circuit of an FET, a resistor and an FET. Gate potentials of FETs are set up by performing addition and subtraction of these reference voltages and a reference voltage generated by a bandgap reference circuit, respectively. The clamp circuit device is constructed by connecting together a source of the one FET with its drain connected with the power supply and a source of the other FET with its drain connected with the ground to an input terminal of a control IC unit. Thus, an input voltage is clamped to [V4+Vtp] when an excessive voltage of positive polarity is applied to an input terminal, and the input voltage is clamped to [V5−Vtn] when an excessive voltage of negative polarity is applied.

摘要翻译： 在钳位电路器件中，参考电压由FET，电阻器和FET的串联电路构成。 通过执行这些参考电压的加法和减法以及由带隙基准电路产生的参考电压来建立FET的栅极电位。 钳位电路器件通过将一个FET的源极与其电源连接在一起而将另一个FET的源极与地线连接到控制IC单元的输入端而构成。 因此，当施加过大的正极性电压到输入端子时，输入电压被钳位到[V 4+ Vtp]，并且当施加负极性的过大电压时，输入电压被钳位到[V 5- Vtn] 。

公开(公告)号：US07890737B2

公开(公告)日：2011-02-15

申请号：US12155017

申请日：2008-05-29

申请人： Naoki Ito ,  Hideaki Ishihara ,  Toshihiko Matsuoka ,  Katsutoyo Misawa

发明人： Naoki Ito ,  Hideaki Ishihara ,  Toshihiko Matsuoka ,  Katsutoyo Misawa

IPC分类号： G06F11/00

CPC分类号： G06F11/26

摘要： A microcomputer for functioning according to operation modes includes; a mode counter that counts the number of times of level change in a signal applied to a mode setting terminal; a mode decoder that decodes output data of the mode counter to output a mode signal, which represents one operation mode; a clock input terminal; a data terminal through which serial data is inputted synchronously with a serial clock signal applied to the clock input terminal; a serial-to-parallel conversion unit that converts the serial data into parallel data and stores the parallel data in an input data buffer; and a switching means that switches to a state that a CPU can access to the input data buffer in a test mode. In the test mode, test instruction data is capable of being inputted from an external circuit.

摘要翻译： 根据操作模式起作用的微型计算机包括： 模式计数器，其对施加到模式设置终端的信号中的电平变化次数进行计数; 解码模式计数器的输出数据以输出表示一种操作模式的模式信号的模式解码器; 时钟输入端子; 数据终端，串行数据与施加到时钟输入端的串行时钟信号同步输入; 串行到并行转换单元，将串行数据转换为并行数据，并将并行数据存储在输入数据缓冲器中; 以及切换装置，切换到CPU能够以测试模式访问输入数据缓冲器的状态。 在测试模式下，能够从外部电路输入测试指令数据。

公开(公告)号：US07631212B2

公开(公告)日：2009-12-08

申请号：US11723434

申请日：2007-03-20

申请人： Katsutoyo Misawa ,  Masato Rinnai ,  Toshihiko Matsuoka ,  Hideaki Ishihara

发明人： Katsutoyo Misawa ,  Masato Rinnai ,  Toshihiko Matsuoka ,  Hideaki Ishihara

IPC分类号： G06F1/08

CPC分类号： H04L12/403 ,  H04L12/10 ,  H04L12/40045 ,  H04L12/66 ,  H04L2012/40273

摘要： A communication system includes: a master; a plurality of slaves; and a bus for coupling among the master and the plurality of slaves in order to communicate asynchronously among the master and the plurality of slaves. The master supplies electricity to the bus in a power supply period. The master or the slave drives the bus for transmitting a one-bit data through the bus in a data transmission period. The power supply period and the data transmission period are successively performed so that data communication provided by a plurality of one-bit periods is performed among the master and the plurality of slaves. The master finely changes a communication frequency in the data communication. The master changes a drive level of the bus within a predetermined acceptable range in the data communication.

摘要翻译： 通信系统包括：主人; 多个奴隶; 以及用于在主机和多个从机之间耦合的总线，以便在主机和多个从机之间异步通信。 主人在供电期间为公共汽车供电。 主器件或从器件在数据传输周期内通过总线驱动总线以发送一位数据。 连续执行电源周期和数据传输周期，使得在主机和多个从机之间执行由多个一比特周期提供的数据通信。 主人精细地改变数据通信中的通信频率。 主机将数据通信中总线的驱动级别改变在预定的可接受范围内。

公开(公告)号：US07519753B2

公开(公告)日：2009-04-14

申请号：US11519014

申请日：2006-09-12

申请人： Katsutoyo Misawa ,  Masato Rinnai ,  Toshihiko Matsuoka ,  Yoshinori Teshima ,  Hideaki Ishihara

发明人： Katsutoyo Misawa ,  Masato Rinnai ,  Toshihiko Matsuoka ,  Yoshinori Teshima ,  Hideaki Ishihara

IPC分类号： G06F13/00

CPC分类号： H04L12/40045 ,  B60R2021/01047 ,  H04L12/403 ,  H04L2012/40273

摘要： A communication system includes a master control unit, a plurality of slave control units, and buses connecting the master control unit and the slave control units for the asynchronous communication. When the master control unit starts the communication, each slave control unit transmits a plurality of data bits represented by whether the buses be driven to the master control unit in data transmission periods assigned to the slave control units based on a start of communication, and the master control unit drives the buses to insert a period for supplying power while data bits are being transmitted in the data transmission period. The slave control unit provides a non-driving period, which stops driving the buses, at an end of the data bit transmission period.

摘要翻译： 通信系统包括主控单元，多个从控单元和连接主控单元和用于异步通信的从控单元的总线。 当主控制单元开始通信时，每个从控制单元基于通信的开始，发送由分配给从控制单元的数据传输期间总线是否被驱动到主控制单元所表示的多个数据位，并且 主控制单元在数据传输期间驱动总线插入一个数据位发送期间供电。 从控制单元在数据位传输周期结束时提供停止驱动总线的非驱动周期。

公开(公告)号：US20070233920A1

公开(公告)日：2007-10-04

申请号：US11723434

申请日：2007-03-20

申请人： Katsutoyo Misawa ,  Masato Rinnai ,  Toshihiko Matsuoka ,  Hideaki Ishihara

发明人： Katsutoyo Misawa ,  Masato Rinnai ,  Toshihiko Matsuoka ,  Hideaki Ishihara

IPC分类号： G06F13/00

CPC分类号： H04L12/403 ,  H04L12/10 ,  H04L12/40045 ,  H04L12/66 ,  H04L2012/40273

摘要： A communication system includes: a master; a plurality of slaves; and a bus for coupling among the master and the plurality of slaves in order to communicate asynchronously among the master and the plurality of slaves. The master supplies electricity to the bus in a power supply period. The master or the slave drives the bus for transmitting a one-bit data through the bus in a data transmission period. The power supply period and the data transmission period are successively performed so that data communication provided by a plurality of one-bit periods is performed among the master and the plurality of slaves. The master finely changes a communication frequency in the data communication. The master changes a drive level of the bus within a predetermined acceptable range in the data communication.

摘要翻译： 通信系统包括：主人; 多个奴隶; 以及用于在主机和多个从机之间耦合的总线，以便在主机和多个从机之间异步通信。 主人在供电期间为公共汽车供电。 主器件或从器件在数据传输周期内通过总线驱动总线以发送一位数据。 连续执行电源周期和数据传输周期，使得在主机和多个从机之间执行由多个一比特周期提供的数据通信。 主人精细地改变数据通信中的通信频率。 主机将数据通信中总线的驱动级别改变在预定的可接受范围内。

公开(公告)号：US07982512B2

公开(公告)日：2011-07-19

申请号：US12585673

申请日：2009-09-22

申请人： Katsutoyo Misawa ,  Masato Rinnai ,  Toshihiko Matsuoka ,  Hideaki Ishihara

发明人： Katsutoyo Misawa ,  Masato Rinnai ,  Toshihiko Matsuoka ,  Hideaki Ishihara

IPC分类号： H03K3/017

CPC分类号： H04L12/403 ,  H04L12/10 ,  H04L12/40045 ,  H04L12/66 ,  H04L2012/40273

摘要： A communication system includes: a master; a plurality of slaves; and a bus for coupling among the master and the plurality of slaves in order to communicate asynchronously among the master and the plurality of slaves. The master supplies electricity to the bus in a power supply period. The master or the slave drives the bus for transmitting a one-bit data through the bus in a data transmission period. The power supply period and the data transmission period are successively performed so that data communication provided by a plurality of one-bit periods is performed among the master and the plurality of slaves. The master finely changes a communication frequency in the data communication. The master changes a drive level of the bus within a predetermined acceptable range in the data communication.

摘要翻译： 通信系统包括：主人; 多个奴隶; 以及用于在主机和多个从机之间耦合的总线，以便在主机和多个从机之间异步通信。 主人在供电期间向公共汽车供电。 主器件或从器件在数据传输周期内通过总线驱动总线以发送一位数据。 连续执行电源周期和数据传输周期，使得在主机和多个从机之间执行由多个一比特周期提供的数据通信。 主人精细地改变数据通信中的通信频率。 主机将数据通信中总线的驱动级别改变在预定的可接受范围内。

公开(公告)号：US07248092B2

公开(公告)日：2007-07-24

申请号：US11073564

申请日：2005-03-08

申请人： Katsutoyo Misawa ,  Yasuyuki Ishikawa ,  Akira Suzuki ,  Yoshinori Teshima ,  Hideaki Ishihara ,  Toshiharu Muramatsu

发明人： Katsutoyo Misawa ,  Yasuyuki Ishikawa ,  Akira Suzuki ,  Yoshinori Teshima ,  Hideaki Ishihara ,  Toshiharu Muramatsu

IPC分类号： H03K5/08

CPC分类号： H03K5/08

摘要： In a clamp circuit device, reference voltages are set up by a series circuit of an FET, a resistor and an FET. Gate potentials of FETs are set up by performing addition and subtraction of these reference voltages and a reference voltage generated by a bandgap reference circuit, respectively. The clamp circuit device is constructed by connecting together a source of the one FET with its drain connected with the power supply and a source of the other FET with its drain connected with the ground to an input terminal of a control IC unit. Thus, an input voltage is clamped to [V4+Vtp] when an excessive voltage of positive polarity is applied to an input terminal, and the input voltage is clamped to [V5−Vtn] when an excessive voltage of negative polarity is applied.

摘要翻译： 在钳位电路器件中，参考电压由FET，电阻器和FET的串联电路构成。 通过执行这些参考电压的加法和减法以及由带隙基准电路产生的参考电压来建立FET的栅极电位。 钳位电路器件通过将一个FET的源极与其电源连接在一起而将另一个FET的源极与地线连接到控制IC单元的输入端而构成。 因此，当施加过大的正极性电压到输入端子时，输入电压被钳位到[V 4+ Vtp]，并且当施加负极性的过大电压时，输入电压被钳位到[V 5- Vtn] 。