公开(公告)号：US5525933A

公开(公告)日：1996-06-11

申请号：US392119

申请日：1995-02-22

申请人： Shigeru Matsuki ,  Kazuhiro Sugita

发明人： Shigeru Matsuki ,  Kazuhiro Sugita

IPC分类号： H03K19/003 ,  H03K5/08 ,  H03K17/16 ,  H03K19/0944

CPC分类号： H03K19/00315

摘要： A semiconductor integrated circuit comprises a signal input terminal, a power supply voltage terminal to which a power voltage is applied, a reference voltage terminal to which a ground voltage is applied, a first PMOS transistor having a drain, a gate connected to the signal input terminal, and a source connected to the power supply voltage terminal, a second PMOS transistor having a gate and a drain being mutually connected to each other, and a source connected to the drain of the first transistor, a third PMOS transistor having a gate connected to the drain of the second transistor, a source connected to the power supply potential terminal, and a drain connected to the drain of the first transistor, an NMOS transistor having a gate connected to the power supply voltage terminal, a drain connected to the drain of the second PMOS transistor, and a source connected to the reference voltage terminal, an internal circuit connected to the drain of the NMOS transistor, a first overvoltage absorption element, connected between the reference voltage terminal and the signal input terminal, for absorbing an overvoltage applied to the signal input terminal, and a second overvoltage absorption element, connected between the signal input terminal and the power supply voltage terminal, for absorbing an overvoltage applied to the signal input terminal.

摘要翻译： 半导体集成电路包括信号输入端子，施加电源电压的电源电压端子，施加接地电压的基准电压端子，具有漏极的第一PMOS晶体管，连接到信号输入端的栅极 端子和连接到电源电压端子的源极，具有彼此相互连接的栅极和漏极的第二PMOS晶体管，以及连接到第一晶体管的漏极的源极，具有栅极连接的第三PMOS晶体管 到第二晶体管的漏极，连接到电源电位端的源极和连接到第一晶体管的漏极的漏极，具有连接到电源电压端子的栅极的NMOS晶体管，连接到漏极的漏极 的第二PMOS晶体管和连接到参考电压端子的源极，连接到NMOS晶体管的漏极的内部电路，第一过电压 吸收元件，连接在参考电压端子和信号输入端子之间，用于吸收施加到信号输入端子的过电压，以及连接在信号输入端子和电源电压端子之间的用于吸收过电压的第二过电压吸收元件 应用于信号输入端子。

公开(公告)号：US4439146A

公开(公告)日：1984-03-27

申请号：US426734

申请日：1982-09-29

申请人： Kazuhiro Sugita

发明人： Kazuhiro Sugita

IPC分类号： H01L21/677 ,  F27B9/30 ,  H01L21/22 ,  F27D5/00 ,  F27B9/00

CPC分类号： H01L21/22 ,  F27B9/3077 ,  Y10S414/137 ,  Y10S414/14

摘要： A heat treatment apparatus is disclosed, which includes a tube device having a tube axis in the horizontal direction for receiving therein an object to be treated so as to treat the same by heat, a holding member for holding thereon a plurality of objects to be treated, first and second supporting devices located at one end outside of the tube device, a first coupling member for coupling the first supporting device with the holding member, a first operating member for moving the holding member in the horizontal direction, a second coupling member attached to the second supporting device for holding a holding portion of the holding member by shaft-rotation, and a second operating member for moving the holding member in the horizontal and vertical directions.

摘要翻译： 公开了一种热处理装置，其包括管装置，该管装置具有在水平方向上的管轴，用于在其中容纳待处理物体以便通过加热处理该物体;保持构件，用于保持多个待处理物体 位于管装置外侧的第一和第二支撑装置，用于将第一支撑装置与保持构件联接的第一联接构件，用于沿水平方向移动保持构件的第一操作构件，附接到第二支撑装置的第二联接构件 通过轴旋转来保持保持构件的保持部的第二支撑装置，以及用于在水平和垂直方向上移动保持构件的第二操作构件。

公开(公告)号：US4103232A

公开(公告)日：1978-07-25

申请号：US645020

申请日：1975-12-29

申请人： Kazuhiro Sugita ,  Chiyohide Kon

发明人： Kazuhiro Sugita ,  Chiyohide Kon

IPC分类号： B25J7/00 ,  G01R1/067 ,  H01L21/677 ,  H01L21/683 ,  H01L21/687 ,  G01R31/22 ,  B65G47/24

CPC分类号： G01R1/06705 ,  B25J7/00 ,  H01L21/67778 ,  H01L21/6835 ,  H01L21/68707 ,  Y10S414/103 ,  Y10S414/137

摘要： A device to facilitate electrical measurement, including step-and-repeat measurement of minute circuits on a semiconductor wafer by placing the wafer in a specific, angular and cartesian coordinate position with respect to a certain orientation of a disc-like pallet of somewhat larger diameter than the wafer. The apparatus includes a stack of available pallets, each having an indexing portion, arms to engage the pallet in turn and to interfit with the indexing portion, a translational motion device to move the arms and pallet to another specific location to receive the wafer, a controllable section device to hold the wafer and to rotate it about a vertical axis, and a further controlled guide device to move the arms and wafer in specific X and Y directions to a predetermined orientation. The device includes a connection between each pallet and an evacuating apparatus to affix the wafer to the pallet by suction when the wafer is released from the suction device on the orienting structure. The apparatus further includes a receiving structure to receive pallets with wafers affixed thereto. In addition, the pallets and wafers are subsequently moved from a stack of untested wafers to testing apparatus that includes probes arranged to engage specific minute areas on the wafers. One of the probes includes electrical contact means to be energized by engagement with the surface of the wafer and to control additional movement of the probes toward the surface to a specific amount to exert a predetermined pressure by the probes on the wafer. After testing, the pallets with tested wafers are moved to a location set aside therefore.

公开(公告)号：US4127969A

公开(公告)日：1978-12-05

申请号：US639806

申请日：1975-12-11

申请人： Kinji Hoshi ,  Kazuhiro Sugita

发明人： Kinji Hoshi ,  Kazuhiro Sugita

IPC分类号： B28D5/00 ,  B28D5/02 ,  B28D5/04 ,  H01L21/00 ,  H01L21/302 ,  H01L29/00 ,  H01L29/06 ,  B24B1/00

CPC分类号： H01L21/02027 ,  B28D5/0058 ,  B28D5/0088 ,  B28D5/022 ,  B28D5/028 ,  B28D5/042 ,  H01L21/302 ,  H01L21/67092 ,  H01L29/00 ,  H01L29/0657

摘要： Semiconductor wafers with apertures, that may include crystal orientation surfaces, are made by boring semiconductor ingots and slicing the bored ingots perpendicular to the bore or at an angle thereto. Novel means are provided for handling the wafers without scratching the major surfaces thereof, for supporting the slices to clean them, and for supporting the slices to coat the major surfaces.

摘要翻译： 可以包括晶体取向表面的具有孔的半导体晶片通过对半导体锭进行钻孔并且将钻孔垂直于孔或与其成一定角度切割。 提供了新颖的装置来处理晶片而不刮擦其主要表面，用于支撑切片以将其清洁，并且用于支撑切片以涂覆主​​表面。