公开(公告)号：US4505024A

公开(公告)日：1985-03-19

申请号：US495409

申请日：1983-05-17

Applicant: Keiichi Kawate ,  Hiroshi Sekiya

Inventor： Keiichi Kawate ,  Hiroshi Sekiya

IPC: H01L21/302 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/78 ,  H01L21/22 ,  H01L21/31

CPC classification number: H01L29/78 ,  H01L21/32136 ,  H01L21/7684

Abstract: A conductor layer is formed on an insulating film which is formed on a semiconductor substrate and which consists of a thick portion and a thin portion with a step therebetween. A film made of material having an etch rate substantially equal to that of the material of the conductor layer is formed on the layer. The film, which has a substantially flat upper surface, and the conductor layer form a laminated structure. Those portions of the laminated structure which are on the thin portion of the insulating film and said step have substantially the same thickness. A mask layer of a predetermined pattern is formed on the laminated structure. Using the mask layer, the laminated structure is selectively etched, the selected portions of the conductor layer and film being etched at the same etching rate. Thereafter, the mask layer and the remaining film are removed.

Abstract translation: 导体层形成在绝缘膜上，该绝缘膜形成在半导体衬底上，并且由绝缘膜和厚壁部分组成，并且其间具有台阶。 在该层上形成由蚀刻速率基本上等于导体层的材料的材料制成的薄膜。 具有基本上平坦的上表面的膜和导体层形成层压结构。 位于绝缘膜的薄壁部分和所述台阶上的层叠结构的那些部分具有基本上相同的厚度。 在叠层结构上形成预定图案的掩模层。 使用掩模层，选择性地蚀刻层压结构，以相同的蚀刻速率蚀刻导体层和膜的选定部分。 此后，除去掩模层和剩余的膜。

公开(公告)号：US4368523A

公开(公告)日：1983-01-11

申请号：US217093

申请日：1980-12-16

Applicant: Keiichi Kawate

Inventor： Keiichi Kawate

IPC: G02F1/1362 ,  G06F11/20 ,  G11C29/00 ,  H01L27/108 ,  G11C5/06 ,  G11C8/02 ,  G11C11/24 ,  H04N5/74

CPC classification number: G06F11/2007 ,  G02F1/13624 ,  G11C29/70 ,  H01L27/108 ,  G02F2001/136263

Abstract: Disclosed is a memory device having a plurality of memory cells arranged in a matrix form; address buses connected to the memory cells and forming respective rows of the matrix; and data buses connected to the memory cells and forming respective columns of the matrix.The address buses or the data buses are formed by paired bus lines, and bridge lines are formed between one and the other of the paired bus lines.

Abstract translation: 公开了具有以矩阵形式布置的多个存储单元的存储器件; 连接到存储器单元并形成矩阵的相应行的地址总线; 以及连接到存储器单元并形成矩阵的相应列的数据总线。 地址总线或数据总线由成对的总线构成，在一对总线之间形成桥接线。