公开(公告)号：US5727194A

公开(公告)日：1998-03-10

申请号：US478438

申请日：1995-06-07

申请人： Avadhani Shridhar ,  Kenichi Nitta

发明人： Avadhani Shridhar ,  Kenichi Nitta

IPC分类号： G06F9/32 ,  G06F9/45 ,  G06F9/30

CPC分类号： G06F8/447 ,  G06F9/325

摘要： A repeat-bit based system and method for executing zero overhead loops, or repeat loops, in an information processing chip that does not require a repeat end register or a dedicated comparator. Executing repeat loops requires a processor to iterate N times a code fragment of loop instructions. All systems providing this capability must know when to refetch the first loop instruction at the end of a repeat. To do this, the present invention adds a repeat bit to the processor's instruction set. This bit is set by the assembler/compiler that generates the executable code fragment comprising the repeat loop. Where the repeat loop includes plural instructions, the assembler sets the repeat bit of the penultimate loop instruction. As each loop instruction is fetched, decoded and executed, the decoder detects the repeat bit and passes it to loop control circuitry. If the code fragment has not been iterated N times and the repeat bit is set, the program counter (PC) is loaded with the address of the first repeat loop instruction, which is refetched. Otherwise, the PC is incremented and the next instruction is fetched. Where the repeat loop has a single instruction, a nop instruction must be added after the instruction to be repeated. Two systems and methods for maintaining the repeat count are disclosed. The first requires a decrementor that decrements the repeat count from N each time the loop is iterated. Another replaces the decrementor with the PC incrementor, which increments the repeat counter from -N or -(N-1).

摘要翻译： 一种基于重复位的系统和方法，用于在不需要重复结束寄存器或专用比较器的信息处理芯片中执行零开销环路或重复循环。 执行重复循环需要处理器重复N次循环指令的代码片段。 提供此功能的所有系统必须知道在重复结束时何时重新获取第一个循环指令。 为此，本发明向处理器的指令集添加重复位。 该位由汇编器/编译器设置，生成包含重复循环的可执行代码段。 在重复循环包括多个指令的地方，汇编器设置倒数第二个循环指令的重复位。 当每个循环指令被取出，解码和执行时，解码器检测重复位并将其传递给环路控制电路。 如果代码片段没有被迭代N次并且重复位被设置，则程序计数器（PC）被加载有第一个重复循环指令的地址，这被重写。 否则，PC将递增，并取下一条指令。 在重复循环具有单个指令的情况下，必须在要重复的指令之后添加nop指令。 公开了用于维持重复计数的两种系统和方法。 第一个需要一个递减器，每次迭代循环时，从N减少重复计数。 另一个用PC增量器代替递减器，该增量器从-N或 - （N-1）增加重复计数器。

公开(公告)号：US5691931A

公开(公告)日：1997-11-25

申请号：US481048

申请日：1995-06-07

申请人： Kenichi Nitta

发明人： Kenichi Nitta

IPC分类号： G06F7/50 ,  G06F7/509 ,  G06F1/00

CPC分类号： G06F7/509 ,  G06F2207/4802

摘要： A low power, adder-based circuit for accumulating small inputs is disclosed. Many applications running on large scale integrated circuits (LSIs) require small, two's complement inputs to be accumulated hundreds, or thousands, of times. Given the number of times such an accumulation is performed, it is essential that the LSI circuitry performing the accumulation operation is power efficient. It is also essential that the accumulator circuitry is compact and not overly complex to keep chip size and cost to a minimum. The present invention includes a input converter that shifts the inputs to be accumulated by a fixed positive amount, yielding a shifted input that is guaranteed to be a positive value. The adder then accumulates the positive shifted inputs. After all of the shifted inputs are accumulated, the adder adds a negative offset to the total to correct for the fixed positive mount added to each of the original inputs. The resulting circuit is power efficient because all of the values accumulated are positive, which minimizes the transition probability of bits manipulated by the adder. The resulting circuit also uses minimal chip real estate as it only needs one adder that performs both accumulation and offset correction.

摘要翻译： 公开了一种用于积累小输入的基于加法器的低功率电路。 许多在大规模集成电路（LSI）上运行的应用需要小的二进制补码输入，可以累积数百或数千次。 给定执行这种累积的次数，执行累积操作的LSI电路是有效的。 同样重要的是，蓄电池电路紧凑，不会过于复杂，从而将芯片尺寸和成本降至最低。 本发明包括一个输入转换器，该输入转换器将要积累的输入移动一个固定的正量，产生保证为正值的移位输入。 然后，加法器累加正移位输入。 在所有移位的输入都被累加之后，加法器将负偏移量添加到总数，以校正添加到每个原始输入的固定正极。 所得到的电路是功率有效的，因为所有积累的值都是正的，这最小化由加法器操纵的位的转移概率。 所得到的电路也使用最小的芯片空间，因为它只需要一个执行积累和偏移校正的加法器。

公开(公告)号：US5372677A

公开(公告)日：1994-12-13

申请号：US991420

申请日：1992-12-16

申请人： Satoshi Katayama ,  Kenichi Nitta ,  Katsuhiko Iimura

发明人： Satoshi Katayama ,  Kenichi Nitta ,  Katsuhiko Iimura

IPC分类号： H01L21/30 ,  G03F7/00 ,  G03F7/40 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/00

CPC分类号： H01L21/31144 ,  G03F7/0035 ,  G03F7/40 ,  H01L21/0274

摘要： After a silicon nitride film (2) is etched by using a first resist pattern (3A) as a mask before coating a second resist (4) superposing on the first resist pattern (3A), a surface layer portion of the first resist pattern (3A) is subjected to a plasma treatment by using oxygen (O.sub.2). A properties changed layer in the surface layer portion of the first resist pattern (3A) is removed or modified to improve the adhesion between the second resist (4) and the first resist pattern (3A), and the stripping of the second resist (4) is prevented.

摘要翻译： 在涂覆叠加在第一抗蚀剂图案（3A）上的第二抗蚀剂（4）之前，通过使用第一抗蚀剂图案（3A）作为掩模蚀刻氮化硅膜（2）之后，将第一抗蚀剂图案的表面层部分 3A）通过使用氧（O 2）进行等离子体处理。 第一抗蚀剂图案（3A）的表层部分中的性质改变层被去除或改性，以改善第二抗蚀剂（4）和第一抗蚀剂图案（3A）之间的粘附性，并且第二抗蚀剂（4）的剥离 ）被阻止。