公开(公告)号：US20110165737A1

公开(公告)日：2011-07-07

申请号：US13064254

申请日：2011-03-14

申请人： Kenichi Yoda

发明人： Kenichi Yoda

IPC分类号： H01L21/82

CPC分类号： H01L27/0207 ,  G06F17/5072 ,  G06F2217/82 ,  H01L27/0248 ,  H01L27/11807

摘要： A method of forming a semiconductor integrated circuit, includes providing a first logic cell, a second logic cell and a metallic wiring connected to the first logic cell and a gate electrode of the second logic cell, and providing a third logic cell including a gate electrode connected to the metallic wiring, such that the third logic cell makes no contribution to a logic operation of the semiconductor integrated circuit, in order that an antenna ratio of the first gate electrode to the metallic wiring does not satisfy an antenna criterion, and an antenna ratio of the first gate electrode and the second gate electrode to the metallic wiring satisfies the antenna criterion.

摘要翻译： 一种形成半导体集成电路的方法，包括：提供连接到第一逻辑单元的第一逻辑单元，第二逻辑单元和连接到第二逻辑单元的栅电极的金属布线，以及提供包括栅电极的第三逻辑单元 连接到金属布线，使得第三逻辑单元对半导体集成电路的逻辑运算没有贡献，以便第一栅电极与金属布线的天线比不满足天线标准，天线 第一栅极电极和第二栅极电极与金属配线的比例满足天线标准。

公开(公告)号：US07741878B2

公开(公告)日：2010-06-22

申请号：US11907212

申请日：2007-10-10

申请人： Kenichi Yoda

发明人： Kenichi Yoda

IPC分类号： H03K19/08 ,  G05F3/02

CPC分类号： H01L27/0207 ,  H01L27/11807

摘要： In a semiconductor integrated circuit, a cell arrangement area is provided on a semiconductor substrate to allow a plurality of basis cells to be arranged. A basic power supply line is provided in an upper layer than the cell arrangement area to supply a power. A switch cell is configured to control the power supply from the basic power supply line to an inside of the cell arrangement area. An always operating cell is arranged in the cell arrangement area adjacently to the switch cell, and is configured to receive the power from the switch cell even when the switch cell stops the power supply to the cell arrangement area.

摘要翻译： 在半导体集成电路中，在半导体基板上设置单元布置区域以允许布置多个单元。 在电池布置区域的上层设置基本电源线以提供电力。 开关单元被配置为控制从基本电源线到电池布置区域的内部的电力供应。 总是工作单元布置在与开关单元相邻的单元布置区域中，并且被配置为即使当开关单元停止向单元布置区域的电力供应时也从开关单元接收电力。

公开(公告)号：US20080087920A1

公开(公告)日：2008-04-17

申请号：US11907212

申请日：2007-10-10

申请人： Kenichi Yoda

发明人： Kenichi Yoda

IPC分类号： H01L27/10

CPC分类号： H01L27/0207 ,  H01L27/11807

摘要： In a semiconductor integrated circuit, a cell arrangement area is provided on a semiconductor substrate to allow a plurality of basis cells to be arranged. A basic power supply line is provided in an upper layer than the cell arrangement area to supply a power. A switch cell is configured to control the power supply from the basic power supply line to an inside of the cell arrangement area. An always operating cell is arranged in the cell arrangement area adjacently to the switch cell, and is configured to receive the power from the switch cell even when the switch cell stops the power supply to the cell arrangement area.

摘要翻译： 在半导体集成电路中，在半导体基板上设置单元布置区域以允许布置多个单元。 在电池布置区域的上层设置基本电源线以提供电力。 开关单元被配置为控制从基本电源线到电池布置区域的内部的电力供应。 总是工作单元布置在与开关单元相邻的单元布置区域中，并且被配置为即使当开关单元停止对单元布置区域的电力供应时也从开关单元接收电力。

公开(公告)号：US4002929A

公开(公告)日：1977-01-11

申请号：US589704

申请日：1975-06-23

申请人： Hideo Suemasa ,  Kazuyoshi Honda ,  Katsuhiko Fukutake ,  Kenichi Yoda

发明人： Hideo Suemasa ,  Kazuyoshi Honda ,  Katsuhiko Fukutake ,  Kenichi Yoda

IPC分类号： H01H47/18 ,  H03K17/292 ,  H03K17/72

CPC分类号： H03K17/292

摘要： Contactless two-line type timer circuit operable stably for a load of even a small current. In the circuit comprising substantially a full-wave rectifying circuit connected through the load to AC source, a thyristor connected across output terminals of the rectifying circuit and means for applying pulses to the gate of the thyristor after a predetermined time period, a first resistance is inserted between the cathode of the thyristor and negative side output terminal of the rectifying circuit and a second resistance is inserted between the gate of the thyristor and said negative side output terminal so as to allow the thyristor to be of a lower gate sensitivity and to be capable of keeping the gate voltage of the thyristor always larger than the cathode voltage.

摘要翻译： 非接触式二线式定时器电路可以稳定地工作，用于甚至是小电流的负载。 在基本上包括通过负载连接到AC源的全波整流电路的电路中，连接在整流电路的输出端上的晶闸管和在预定时间段之后向晶闸管的栅极施加脉冲的装置，第一电阻为 插入在晶闸管的阴极和整流电路的负侧输出端子之间，并且在晶闸管的栅极和所述负侧输出端子之间插入第二电阻，以允许晶闸管具有较低的栅极灵敏度，并且为 能够保持晶闸管的栅极电压总是大于阴极电压。

公开(公告)号：US08384163B2

公开(公告)日：2013-02-26

申请号：US13006659

申请日：2011-01-14

申请人： Kenichi Yoda

发明人： Kenichi Yoda

IPC分类号： H01L27/092 ,  H01L21/70 ,  H01L27/088 ,  H01L29/02 ,  H01L27/118

CPC分类号： H01L27/0207 ,  G06F17/5068 ,  H01L27/11807

摘要： Design time (TAT) is reduced in a layout design of a semiconductor integrated circuit having a well supplied with a potential different from a substrate potential. A layout design method of the present invention includes preparing a first cell pattern placed on a semiconductor substrate of a first conductive type, preparing a second cell pattern having a deep well of a second conductive type, placing the first cell pattern in a first circuit region, and placing the second cell pattern in a second region different from the first circuit region. This reduces TAT in chip design.

摘要翻译： 设计时间（TAT）在具有不同于衬底电位的电位的半导体集成电路的布局设计中被减少。 本发明的布局设计方法包括制备放置在第一导电类型的半导体衬底上的第一单元图案，制备具有第二导电类型的深阱的第二单元图案，将第一单元图案放置在第一电路区域中 并且将第二单元图案放置在与第一电路区域不同的第二区域中。 这减少了芯片设计中的TAT。

公开(公告)号：US20110113391A1

公开(公告)日：2011-05-12

申请号：US13006659

申请日：2011-01-14

申请人： Kenichi YODA

发明人： Kenichi YODA

IPC分类号： G06F17/50

CPC分类号： H01L27/0207 ,  G06F17/5068 ,  H01L27/11807

摘要： Design time (TAT) is reduced in a layout design of a semiconductor integrated circuit having a well supplied with a potential different from a substrate potential. A layout design method of the present invention includes preparing a first cell pattern placed on a semiconductor substrate of a first conductive type, preparing a second cell pattern having a deep well of a second conductive type, placing the first cell pattern in a first circuit region, and placing the second cell pattern in a second region different from the first circuit region. This reduces TAT in chip design.

摘要翻译： 设计时间（TAT）在具有不同于衬底电位的电位的半导体集成电路的布局设计中被减少。 本发明的布局设计方法包括制备放置在第一导电类型的半导体衬底上的第一单元图案，制备具有第二导电类型的深阱的第二单元图案，将第一单元图案放置在第一电路区域中 并且将第二单元图案放置在与第一电路区域不同的第二区域中。 这减少了芯片设计中的TAT。

公开(公告)号：US4395136A

公开(公告)日：1983-07-26

申请号：US223326

申请日：1981-01-08

申请人： Kenichi Yoda ,  Hideo Togawa ,  Eizou Ogawa ,  Masao Kayahara

发明人： Kenichi Yoda ,  Hideo Togawa ,  Eizou Ogawa ,  Masao Kayahara

IPC分类号： H03K5/135 ,  G04F1/00 ,  G04G3/02 ,  H03K17/22 ,  H03K17/28 ,  G06F1/04

CPC分类号： H03K17/28 ,  G04F1/005 ,  G04G3/02

摘要： An electronic timer wherein a counting circuit for counting outputs of a CR oscillating circuit comprises a plurality of partial counting circuits which are cascade-connected with one another, the respective partial counting circuits are automatically reset by an automatic resetting circuit when a source current voltage is applied or reset by an external resetting circuit at a desired time, the outputs of the CR oscillating circuit are counted by the respective partial counting circuits after the resetting, and a following output circuit is driven when the count reaches an externally set value of a setting circuit. The partial counting circuits are divided into groups by an external driving test circuit to quickly test the operation of the counting circuit.

摘要翻译： 一种电子定时器，其中用于计数CR振荡电路的输出的计数电路包括彼此级联的多个部分计数电路，当源电流电压为 通过外部复位电路在期望的时间施加或复位，CR振荡电路的输出由复位后的各个部分计数电路进行计数，并且当计数达到设定值的外部设定值时驱动跟随的输出电路 电路。 部分计数电路由外部驱动测试电路分成组，以快速测试计数电路的运行。

公开(公告)号：US07884426B2

公开(公告)日：2011-02-08

申请号：US11591550

申请日：2006-11-02

申请人： Kenichi Yoda

发明人： Kenichi Yoda

IPC分类号： H01L27/092 ,  H01L21/70 ,  H01L27/088 ,  H01L29/02 ,  H01L27/118

CPC分类号： H01L27/0207 ,  G06F17/5068 ,  H01L27/11807

摘要： Design time (TAT) is reduced in a layout design of a semiconductor integrated circuit having a well supplied with a potential different from a substrate potential. A layout design method of the present invention includes preparing a first cell pattern placed on a semiconductor substrate of a first conductive type, preparing a second cell pattern having a deep well of a second conductive type, placing the first cell pattern in a first circuit region, and placing the second cell pattern in a second region different from the first circuit region. This reduces TAT in chip design.

摘要翻译： 设计时间（TAT）在具有不同于衬底电位的电位的半导体集成电路的布局设计中被减少。 本发明的布局设计方法包括制备放置在第一导电类型的半导体衬底上的第一单元图案，制备具有第二导电类型的深阱的第二单元图案，将第一单元图案放置在第一电路区域中 并且将第二单元图案放置在与第一电路区域不同的第二区域中。 这减少了芯片设计中的TAT。

公开(公告)号：US20100138803A1

公开(公告)日：2010-06-03

申请号：US12625968

申请日：2009-11-25

申请人： Tetsuro Minamiyama ,  Kenichi Yoda

发明人： Tetsuro Minamiyama ,  Kenichi Yoda

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5045

摘要： A method of supporting design of a semiconductor integrated circuit, is achieved by generating a data indicating a basic cell and a data indicating a cell group different in logic from the basic cell; and by storing the basic cell indicating data and the cell group indicating data in a library of a storage unit. An outer shape and a position of a wiring pattern of the cell group are same as those of the basic cell. The wiring pattern of the basic cell and the wiring pattern of the cell group contain a wiring obstruction section indicating an area in which a passage wiring is inhibited. When a design change is carried out, the basic cell is replaced by a change cell of the cell group corresponding to the design change.

摘要翻译： 一种支持半导体集成电路设计的方法是通过生成指示基本单元的数据和指示与基本单元不同的逻辑单元组的数据来实现的; 并且通过将基本信元指示数据和信元组指示数据存储在存储单元的库中。 单元组的布线图案的外形和位置与基本单元的外形和位置相同。 基体单元的布线图案和单元组的布线图案包含指示通过布线被禁止的区域的布线障碍部。 当进行设计更改时，基本单元被替换为与设计变更相对应的单元组的改变单元。

公开(公告)号：US20100001403A1

公开(公告)日：2010-01-07

申请号：US12458150

申请日：2009-07-01

申请人： Kenichi Yoda

发明人： Kenichi Yoda

IPC分类号： H01L23/52 ,  G06F17/50 ,  H01L21/768 ,  H01L21/50

CPC分类号： H01L27/0207 ,  G06F17/5072 ,  G06F2217/82 ,  H01L27/0248 ,  H01L27/11807

摘要： A method of designing a semiconductor integrated circuit, includes verifying an antenna ratio of a metallic wiring connected to a first gate electrode and the first gate electrode, based on a layout information, and computing a gate area that should be added to avoid a plasma damage to the first gate electrode, based on the verifying. The method further includes modifying a layout of the semiconductor integrated circuit, based on the computing, by arranging a logic cell having a second gate electrode having the gate area or more and is in a state where the logic cell makes no contribution to a logic operation of the semiconductor integrated circuit, in a free region of the layout, and connecting the second gate electrode to the metallic wiring.

摘要翻译： 一种设计半导体集成电路的方法，包括基于布局信息来验证连接到第一栅电极和第一栅电极的金属布线的天线比，以及计算应加入的栅极面积以避免等离子体损伤 到第一栅电极，基于验证。 该方法还包括：通过布置具有栅极面积以上的第二栅电极的逻辑单元，并且处于逻辑单元对逻辑运算无贡献的状态，通过计算来修正半导体集成电路的布局 的半导体集成电路，在布局的自由区域中，并且将第二栅电极连接到金属布线。