公开(公告)号：US4531119A

公开(公告)日：1985-07-23

申请号：US676597

申请日：1984-11-30

申请人： Takeshi Nakayama ,  Masaaki Kurosu ,  Yoshimitsu Ohshima ,  Kenji Fujikata ,  Shigeru Uchida ,  Akira Nakajima

发明人： Takeshi Nakayama ,  Masaaki Kurosu ,  Yoshimitsu Ohshima ,  Kenji Fujikata ,  Shigeru Uchida ,  Akira Nakajima

IPC分类号： G06F17/22 ,  G06F3/00 ,  G06F3/01 ,  G06F15/38

CPC分类号： G06F3/018

摘要： A method and apparatus for selectively key-inputting a Kanji (Chinese and Japanese ideogram) in a Japanese sentence are disclosed. The operator keys-in a reading of a desired Kanji through a keyboard, and candidate Kanjis for that reading are displayed on a display screen so that the operator chooses a relevant Kanji for entry out of the displayed candidate Kanjis. In entering the reading of a Kanji, blocks which are in correspondence to character keys located in home positions of the keyboard and in the neighborhood thereof are displayed on the display screen and candidate Kanjis corresponding to the reading of the desired Kanji are displayed in the blocks. The operator then keys a character key corresponding to a relevant candidate Kanji displayed on the display screen.

摘要翻译： 公开了一种用于在日语句子中选择性地键入汉字（中文和日文表意文字）的方法和装置。 操作员按键 - 通过键盘对所需汉字的读数和用于该读数的候选Kanjis显示在显示屏幕上，使得操作者选择相关汉字进入所显示的候选Kanjis。 在进入汉字的读数时，显示屏上显示与位于键盘的原始位置和附近的字符键相对应的块，并将与期望的汉字的读取对应的候补Kanjis显示在块 。 然后，操作者键入与显示在显示屏上的相关候选汉字对应的字符键。

公开(公告)号：US4197486A

公开(公告)日：1980-04-08

申请号：US842155

申请日：1977-10-14

申请人： Atsushi Iwata ,  Minpei Fujinami ,  Akinori Shibayama ,  Norio Yokozawa ,  Kenji Maio ,  Kenji Fujikata

发明人： Atsushi Iwata ,  Minpei Fujinami ,  Akinori Shibayama ,  Norio Yokozawa ,  Kenji Maio ,  Kenji Fujikata

IPC分类号： H01J37/147 ,  G09G1/08 ,  H01L21/027 ,  H04N3/16 ,  H01J29/70 ,  H01J29/72

CPC分类号： G09G1/08

摘要： An electron beam deflection control system includes a first signal generation circuit which generates a triangular signal varying at a comparatively low speed, a second signal generation circuit which generates a stepped signal varying at a comparatively high speed, and a switching arrangement to change over the first and second signal generation circuits and to drive one of them, whereby the signal from the generation circuit selected by the switching arrangement is used as a deflection signal for an electron beam.

摘要翻译： 一种电子束偏转控制系统，包括产生以较低速度变化的三角形信号的第一信号发生电路，产生以较高速度变化的阶梯式信号的第二信号发生电路，以及切换装置， 和第二信号发生电路，并驱动它们之一，由此将由开关装置选择的发电电路的信号用作电子束的偏转信号。

公开(公告)号：US4161700A

公开(公告)日：1979-07-17

申请号：US853885

申请日：1977-11-22

申请人： Kenji Fujikata ,  Norio Yokozawa ,  Akinori Shibayama

发明人： Kenji Fujikata ,  Norio Yokozawa ,  Akinori Shibayama

IPC分类号： G01R19/00 ,  G01R19/165 ,  G01R19/32 ,  G05B1/02 ,  H03K5/08 ,  H03K5/15 ,  H03K5/153

CPC分类号： G05B1/02 ,  G01R19/16585

摘要： An analog comparator comprising a generator circuit which generates an input signal voltage having a certain slew rate, a setting circuit which sets a target or desired voltage, another setting circuit which sets a threshold voltage corresponding to the slew rate of the input signal voltage and an ambient temperature, and a comparison circuit which receives the input signal voltage, the target voltage and the threshold voltage and which delivers a coincidence timing signal upon detecting that the input signal voltage has reached a voltage shifting by the threshold voltage from the target voltage.

摘要翻译： 一种模拟比较器，包括产生具有一定转换速率的输入信号电压的发生器电路，设定目标或期望电压的设定电路，设定与输入信号电压的转换速率对应的阈值电压的另一设定电路，以及 以及比较电路，其接收输入信号电压，目标电压和阈值电压，并且在检测到输入信号电压已经达到从目标电压的阈值电压偏移的电压时传送符合定时信号。

公开(公告)号：US4748558A

公开(公告)日：1988-05-31

申请号：US858791

申请日：1986-05-01

申请人： Toshio Hirosawa ,  Kazumitu Kondo ,  Katsuto Miyazaki ,  Kenji Fujikata

发明人： Toshio Hirosawa ,  Kazumitu Kondo ,  Katsuto Miyazaki ,  Kenji Fujikata

IPC分类号： G06F15/16 ,  G06F9/50 ,  G06F15/177

CPC分类号： G06F9/505

摘要： A loosely coupled multi-processor system including a plurality of terminals and corresponding processors. When a particular terminal tries to start a program, the corresponding processor sets the largest number of the terminals, which are serviceable, on the basis of the load status of the processors which are permanently watched by the OS (operating system) in a main memory. The processor compares this largest number with the number of terminals, which are in service at that time and when the number of the terminals, which are in service, is smaller than the largest number, processing by the terminal issuing a service demand begins. Alternatively, when the number of the terminals, which are in service, is equal to or greater than the largest number, the processor cannot treat the service demand from the terminal and reports this to a global processor. The global processor examines the load status indicator contained therein which shows the load status of each of the system processors; selects the processor having the lightest load status; and issues an order to treat the service demand from the requesting terminal to the selected processor having the lightest load. The processor, which has received the order, performs the processing of the service demand from the requesting terminal, based on the instruction from the global processor.

摘要翻译： 松散耦合的多处理器系统包括多个终端和相应的处理器。 当特定终端尝试启动程序时，相应的处理器基于由主存储器中的OS（操作系统）永久监视的处理器的负载状态来设置可维护的终端的最大数量 。 处理器将此最大数量与当时正在使用的终端数量进行比较，并且当服务中的终端的数量小于最大数量时，由终端发出服务需求的处理开始。 或者，当正在使用的终端的数量等于或大于最大数量时，处理器不能处理来自终端的服务需求并将其报告给全局处理器。 全局处理器检查其中包含的负载状态指示器，其中显示每个系统处理器的负载状态; 选择具有最轻负载状态的处理器; 并且发出将请求终端的服务需求视为具有最轻负载的所选处理器的命令。 已经接收到订单的处理器基于来自全局处理器的指令执行来自请求终端的服务需求的处理。

公开(公告)号：US4051457A

公开(公告)日：1977-09-27

申请号：US655139

申请日：1976-02-03

申请人： Fumiyuki Inose ,  Kenji Fujikata ,  Norio Yokozawa

发明人： Fumiyuki Inose ,  Kenji Fujikata ,  Norio Yokozawa

IPC分类号： G11B20/00 ,  G06F3/153 ,  G06K15/10 ,  G09G1/02 ,  G09G5/24 ,  H03M7/00 ,  G11C15/00

CPC分类号： H03M7/001 ,  G09G1/02

摘要： In a character displaying device having a character pattern memory which is made up of a circulating sequential access memory storing character patterns therein, a character pattern generating system comprises a high speed buffer memory which stores the character codes of one line or any other suitable amount of characters to be displayed and the corresponding character patterns, so that each time one character is delivered as an output from the character pattern memory, the presence of the character code of the particular character is examined for all the character codes of the buffer memory, and the character pattern of the particular character is written into the buffer memory when the character codes are coincident, the writing operations being sequentially executed in the order of the character outputs of the character pattern memory, thereby making it possible to finish all the character patterns in the buffer memory within a period in which the read-out of the character pattern memory circulates.