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公开(公告)号：US20090085067A1
公开(公告)日：2009-04-02
申请号：US12325697
申请日：2008-12-01
申请人： Kohtaro HAYASHI , Akinori Shibayama
发明人： Kohtaro HAYASHI , Akinori Shibayama
IPC分类号： H01L27/088
CPC分类号： G06F17/5072 , H01L27/0207
摘要： A layout design method for a semiconductor device includes a step of arranging transistors, a dummy gate forming step of forming dummy gates, which has a shape identical with a shape including gate electrodes or the gate electrodes and projected parts from active regions of the gate electrodes, in positions in parallel with and a fixed distance apart from the gate electrodes arranged at both ends in a gate length direction on active regions of the transistors and, when the transistors have plural gate electrodes with different gate widths, extending the projected parts to the outside of the active regions by a necessary length, a gate connecting step of, when gate patterns and contact regions are connected to the gate electrodes of the transistors, connecting the gate electrodes and the dummy gates according to a positional relation between the gate electrodes and the dummy gates, and a wiring step of wiring a metal layer. It is possible to design a semiconductor device having a smaller area than that in the past and with a less design man-hour.
摘要翻译： 一种用于半导体器件的布局设计方法包括：布置晶体管的步骤，形成伪栅极的伪栅极形成步骤，其具有与包括栅电极或栅电极的形状相同的形状以及从栅电极的有源区域的突出部分 在与晶体管的有源区域的栅极长度方向上配置的栅极电极平行且固定距离的位置上，并且当晶体管具有多个具有不同栅极宽度的栅电极时，将投影部分延伸到 在有源区域外部具有必要的长度;栅极连接步骤，当栅极图案和接触区域连接到晶体管的栅电极时，根据栅电极和栅电极之间的位置关系连接栅电极和伪栅极; 虚拟栅极和布线金属层的布线步骤。 可以设计具有比过去小的面积和较少设计工时的半导体器件。
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公开(公告)号：US07469396B2
公开(公告)日：2008-12-23
申请号：US11149350
申请日：2005-06-10
申请人： Kohtaro Hayashi , Akinori Shibayama
发明人： Kohtaro Hayashi , Akinori Shibayama
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , H01L27/0207
摘要： A layout design method for a semiconductor device includes a step of arranging transistors, a dummy gate forming step of forming dummy gates, which has a shape identical with a shape including gate electrodes or the gate electrodes and projected parts from active regions of the gate electrodes, in positions in parallel with and a fixed distance apart from the gate electrodes arranged at both ends in a gate length direction on active regions of the transistors and, when the transistors have plural gate electrodes with different gate widths, extending the projected parts to the outside of the active regions by a necessary length, a gate connecting step of, when gate patterns and contact regions are connected to the gate electrodes of the transistors, connecting the gate electrodes and the dummy gates according to a positional relation between the gate electrodes and the dummy gates, and a wiring step of wiring a metal layer. It is possible to design a semiconductor device having a smaller area than that in the past and with a less design man-hour.
摘要翻译： 一种用于半导体器件的布局设计方法包括：布置晶体管的步骤，形成伪栅极的伪栅极形成步骤，其具有与包括栅电极或栅电极的形状相同的形状以及从栅电极的有源区域的突出部分 在与晶体管的有源区域的栅极长度方向上配置的栅极电极平行且固定距离的位置上，并且当晶体管具有多个具有不同栅极宽度的栅电极时，将投影部分延伸到 在有源区域外部具有必要的长度;栅极连接步骤，当栅极图案和接触区域连接到晶体管的栅电极时，根据栅电极和栅电极之间的位置关系连接栅电极和伪栅极; 虚拟栅极和布线金属层的布线步骤。 可以设计具有比过去小的面积和较少设计工时的半导体器件。
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公开(公告)号：US06937532B2
公开(公告)日：2005-08-30
申请号：US10628168
申请日：2003-07-28
IPC分类号： G11C11/413 , G11C5/02 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/8242 , H01L21/8244 , H01L27/108 , H01L27/11 , G11C7/00
摘要： A semiconductor memory includes a memory cell array, a redundancy repair signal generator, and a row decoder. The memory cell array includes a plurality of memory cell rows and at least one redundant memory cell row. The redundancy repair signal generator generates a redundancy repair signal that indicates an address of a defective memory cell row. The row decoder receives a row address signal that indicates a memory cell row including a memory cell to be accessed and selects the redundant memory cell row in accordance with the redundancy repair signal generated by the redundancy repair signal generator. The redundancy repair signal generator is located opposite to the row decoder with the memory cell array placed therebetween. This configuration can achieve a reduction in free space and thus a reduction in area loss.
摘要翻译： 半导体存储器包括存储单元阵列，冗余修复信号发生器和行解码器。 存储单元阵列包括多个存储单元行和至少一个冗余存储单元行。 冗余修复信号发生器产生指示有缺陷的存储器单元行的地址的冗余修复信号。 行解码器接收指示包括要访问的存储单元的存储单元行的行地址信号，并根据由冗余修复信号发生器产生的冗余修复信号选择冗余存储单元行。 冗余修复信号发生器位于与行解码器相对的位置，存储单元阵列位于它们之间。 这种构造可以实现自由空间的减小，从而减少面积损耗。
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公开(公告)号：US20050041499A1
公开(公告)日：2005-02-24
申请号：US10902133
申请日：2004-07-30
申请人： Akinori Shibayama
发明人： Akinori Shibayama
IPC分类号： G11C11/41 , G11C11/412 , H01L21/8244 , H01L27/11 , G11C7/02
CPC分类号： G11C11/412 , H01L27/11
摘要： A semiconductor memory device according to the present invention includes: a plurality of N-ch MOS transistors arranged in an area surrounding a plurality of memory cells arranged in an array, at a spacing depending on a spacing of the plurality of memory cells, for driving the plurality of memory cells; and a plurality of dummy transistors 32-j each of which is formed between two adjacent ones of the plurality of N-ch MOS transistors 30-k so as to share diffusion layers with adjacent N-ch MOS transistors 30 and each of which has a gate electrode supplied with a voltage for electrically insulating these adjacent transistors 30-k.
摘要翻译： 根据本发明的半导体存储器件包括：多个N沟道MOS晶体管，其布置在以阵列布置的多个存储单元的区域中，其间隔取决于多个存储单元的间隔，用于驱动 所述多个存储单元; 以及分别形成在多个N沟道MOS晶体管30-k中的两个相邻的N沟道MOS晶体管30-k之间的多个虚设晶体管32-j，以便与相邻的N沟道MOS晶体管30共享扩散层，并且每个具有 栅电极被提供有用于使这些相邻晶体管30-k电绝缘的电压。
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公开(公告)号：US06597621B2
公开(公告)日：2003-07-22
申请号：US09791778
申请日：2001-02-26
申请人： Takaharu Tsuji , Akinori Shibayama
发明人： Takaharu Tsuji , Akinori Shibayama
IPC分类号： G11C700
CPC分类号： G11C8/12 , G11C11/4085 , G11C11/4087
摘要： In a semiconductor memory device with a plurality of banks having a plurality of memory sub array, according to a mode setting signal, data access control is made depending on whether access is made on a memory sub array basis or a bank basis. A multi-bank semiconductor memory device is provided capable of easily implementing both of a low power consumption mode and a long page size mode.
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公开(公告)号：US5773968A
公开(公告)日：1998-06-30
申请号：US716786
申请日：1996-09-11
申请人： Hideaki Kondo , Akinori Shibayama
发明人： Hideaki Kondo , Akinori Shibayama
IPC分类号： G05F3/24 , G05F1/46 , G05F1/56 , G11C11/407 , G05F3/16
CPC分类号： G05F1/465
摘要： A voltage conversion circuit that includes a reference voltage generation circuit, an output circuit, and an output control circuit. The reference voltage generation circuit outputs a first reference voltage and a second reference voltage which is higher than the first reference voltage by a predetermined voltage. Based on the first reference voltage, the output circuit outputs an internally converted voltage. The output control circuit reduces the internally converted voltage when the control circuit outputs a higher internally converted voltage than the second reference voltage. In accordance with the voltage conversion circuit, even when there occurs an increase in the internally converted voltage due to the flow of very small leakage currents between an external power supply and the internal voltage conversion circuit, the internally converted voltage is lowered by the output control circuit when it exceeds the second reference voltage output from the reference voltage generation circuit. This prevents an excess increase in the internally converted voltage, which ensures that internal elements in the semiconductor integrated circuit can be fed a stable voltage.
摘要翻译： 一种电压转换电路，包括参考电压产生电路，输出电路和输出控制电路。 参考电压产生电路输出比第一参考电压高一预定电压的第一参考电压和第二参考电压。 基于第一参考电压，输出电路输出内部转换的电压。 当控制电路输出比第二参考电压更高的内部转换电压时，输出控制电路减小内部转换的电压。 根据电压转换电路，即使由于外部电源和内部电压转换电路之间的非常小的漏电流的流动而发生内部转换电压的增加，内部转换的电压也被输出控制 当它超过从参考电压产生电路输出的第二参考电压时。 这防止内部转换的电压的过度增加，这确保了半导体集成电路中的内部元件能够被馈送稳定的电压。
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公开(公告)号：US5248936A
公开(公告)日：1993-09-28
申请号：US767998
申请日：1991-09-30
CPC分类号： G01R31/2884
摘要： A semiconductor integrated circuit has a main circuit (1), a self testing circuit (2) for testing the main circuit (1), a test start signal detection circuit (5) having at least one light sensitive device for detecting a test start signal in the form of light, and a test result output circuit (4) having at least one light emitting device for outputting test results from the self testing circuit (2) in the form of light. A drastic reduction in test time is accomplished by applying the test start signal in a non-contacting manner to the semiconductor integrated circuit so as to activate the self testing circuit. Furthermore, the test result is output to the outside of the semiconductor integrated circuit without having to provide electrical connections, and the simultaneous testing of a greater number of semiconductor integrated circuits as formed on the same wafer can be accomplished.
摘要翻译： 半导体集成电路具有主电路（1），用于测试主电路（1）的自检电路（2），具有至少一个用于检测测试开始信号的光敏装置的测试开始信号检测电路（5） 以及具有至少一个发光装置的测试结果输出电路（4），用于以光的形式从自检电路（2）输出测试结果。 通过将测试开始信号以非接触的方式施加到半导体集成电路以激活自检电路来实现测试时间的急剧减少。 此外，测试结果输出到半导体集成电路的外部，而不必提供电连接，并且可以实现在同一晶片上形成的更多数量的半导体集成电路的同时测试。
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公开(公告)号：US5177448A
公开(公告)日：1993-01-05
申请号：US616844
申请日：1990-11-21
申请人： Takashi Ikeguchi , Manabu Matsumoto , Shinjiroo Ueda , Tadasi Sonobe , Toru Murashita , Satoshi Ido , Kazuo Kuroichi , Akinori Shibayama
发明人： Takashi Ikeguchi , Manabu Matsumoto , Shinjiroo Ueda , Tadasi Sonobe , Toru Murashita , Satoshi Ido , Kazuo Kuroichi , Akinori Shibayama
IPC分类号： H05H7/00
CPC分类号： H05H7/00
摘要： An industrial compact synchrotron radiation source includes, for the purpose of prolonging lifetime of a charged particle beam, beam absorbers made of a material having a low photodesorption yield and disposed inside a bending section/vacuum chamber at at least positions upon which the synchrotron radiation is irradiated, and electrically conductive beam stabilizers disposed at positions inside the bending section/vacuum chamber which are distant by a predetermined distance from an orbit of the charged particle beam toward the outer circumferential wall of the bending section/vacuum chamber.
摘要翻译： 为了延长带电粒子束的使用寿命，工业致密同步加速器辐射源包括由具有低光解吸收率的材料制成的光束吸收器，并且设置在至少位置上的弯曲部分/真空室内，同步加速器辐射为 照射和导电的光束稳定器，其设置在弯曲部分/真空室内部位于与带电粒子束的轨道相距预定距离的位置处，弯曲部分/真空室的外周壁。
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公开(公告)号：US4992745A
公开(公告)日：1991-02-12
申请号：US277989
申请日：1988-11-30
CPC分类号： H05H7/02
摘要： When accelerating charged particles on synchrotron acceleration basis by using a circular accelerator having a RF acceleration cavity, the detuned amount representative of an offset between oscillation frequency of a RF oscillator for the RF acceleration cavity and resoance frequency of the RF acceleration cavity and the RF power for supplying the charged particles with energy are controlled in compliance with changes in energy of the charged particles without changing the oscillation frequency. A great number of charged particles injected into the circular accelerator can be accelerated to the ultimate storage energy during the acceleration on synchrotron acceleration basis without causing charged particle beam loss.
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公开(公告)号：US4835535A
公开(公告)日：1989-05-30
申请号：US22483
申请日：1987-03-06
CPC分类号： G05B19/231 , H03M1/1071 , H03M1/745
摘要： In a D/A converting apparatus which provides a converted analog signal at its output terminal by selectively yielding one or more currents from one or more current sources in accordance with an input digital signal, the current sources are selectively actuated to output the currents and an error in the current of each selected current source is obtained from the output derived at the output terminal in response to the outputting of the current. From the current error of each current source is computed a final error corresponding to each input digital signal and corrected data corresponding to the final error is stored in a corrected data memory, which is read out by the input digital signal. The output thus read out is converted into an analog signal, whereby a correct converted output is obtained.
摘要翻译： 在D / A转换装置中，通过根据输入数字信号选择性地产生来自一个或多个电流源的一个或多个电流，在其输出端提供转换的模拟信号，电流源被选择性地致动以输出电流和 响应于输出电流，从输出端导出的输出获得每个选定电流源的电流的误差。 从每个电流源的当前误差计算出与每个输入数字信号相对应的最终误差，并且对应于最终误差的校正数据被存储在由输入数字信号读出的校正数据存储器中。 由此读出的输出被转换为模拟信号，由此获得正确的转换输出。
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