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公开(公告)号：US20080059770A1
公开(公告)日：2008-03-06
申请号：US11730566
申请日：2007-04-02
申请人： Sanjiv Garg , Kevin Iadonato , Le Nguyen , Johannes Wang
发明人： Sanjiv Garg , Kevin Iadonato , Le Nguyen , Johannes Wang
IPC分类号： G06F9/312
CPC分类号： G06F9/3013 , G06F9/3824 , G06F9/3838 , G06F9/384 , G06F9/3855
摘要： A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.
摘要翻译： 一种用于无序执行一组具有可寻址源和目的寄存器字段的精简指令集计算机指令的寄存器重命名系统，适用于具有指令执行单元的计算机，该指令执行单元具有通过读地址端口访问的寄存器文件， 存储指令操作数。 包括数据相关性检查电路，用于确定指令之间的数据依赖性。 标签分配电路基于由数据相关性检查电路确定的数据依赖性，生成一个或多个标签以指定操作数的位置。 一组寄存器文件端口复用器选择标签分配电路产生的标签，并将标签传递到寄存器文件的读取地址端口，以存储执行结果。
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公开(公告)号：US06418528B1
公开(公告)日：2002-07-09
申请号：US09131881
申请日：1998-08-10
IPC分类号： G06F9302
CPC分类号： G06F9/3885 , G06F9/30149 , G06F9/3861
摘要： An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.
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公开(公告)号：US5860000A
公开(公告)日：1999-01-12
申请号：US594763
申请日：1996-01-31
CPC分类号： G06F9/3885 , G06F9/30149 , G06F9/3861
摘要： An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.
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4.发明申请公开(公告)号：US20060123218A1
公开(公告)日：2006-06-08
申请号：US11338817
申请日：2006-01-25
申请人： Kevin Iadonato , Trevor Deosaran , Sanjiv Garg
发明人： Kevin Iadonato , Trevor Deosaran , Sanjiv Garg
IPC分类号： G06F15/00
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3885
摘要： A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each instruction. A queue having a plurality of slots containing tags which are used for tagging the instructions. The tags are arranged in the queue in an order specified by the program order of their corresponding instructions. A control unit monitors the completion of executed instructions and advances the tags in the queue upon completion of an executed instruction. The register file stores an instruction's information at a location in the register file defined by the tag assigned to that instruction. The register file also contains a plurality of read address enable ports and corresponding read output ports. Each of the slots from the queue is coupled to a corresponding one of the read address enable ports. Thus, the information for each instruction can be read out of the register file in program order.
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公开(公告)号：US20060020773A1
公开(公告)日：2006-01-26
申请号：US11235090
申请日：2005-09-27
申请人： Trevor Deosaran , Sanjiv Garg , Kevin Iadonato
发明人： Trevor Deosaran , Sanjiv Garg , Kevin Iadonato
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/384 , G06F9/3857
摘要： A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a location becomes available. A tag is assigned to each instruction in the variable advance instruction window. The tag of each instruction to leave the window is assigned to the next new instruction to be added to it. The results of instructions executed by the processor are stored in a temp buffer according to their corresponding tags to avoid output and anti-dependencies. The temp buffer therefore permits the processor to execute instructions out of order and in parallel. Data dependency checks for input dependencies are performed only for each new instruction added to the variable advance instruction window and register renaming is performed to avoid input dependencies.
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公开(公告)号：US07162616B2
公开(公告)日：2007-01-09
申请号：US10796552
申请日：2004-03-08
IPC分类号： G06F9/312
CPC分类号： G06F9/3885 , G06F9/30149 , G06F9/3861
摘要： An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.
摘要翻译： FPU流水线与CPU流水线同步。 通过在任何一个管道中进行停顿和冻结来实现同步，从而在另一个管道中停顿并冻结。 即使长时间浮点运算，异常也保持精确。 当第一个浮点指令进入FPU流水线的第一个执行阶段时，通过使FPU流水线的第一个执行阶段产生一个忙信号来实现精确的例外。 当第一个浮点指令在FPU流水线的第一阶段完成执行之前，FPU流水线进行第二个浮点指令解码时，两条流水线停顿。
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公开(公告)号：US20060041736A1
公开(公告)日：2006-02-23
申请号：US11252820
申请日：2005-10-19
申请人： Sanjiv Garg , Kevin Iadonato , Le Nguyen , Johannes Wang
发明人： Sanjiv Garg , Kevin Iadonato , Le Nguyen , Johannes Wang
CPC分类号： G06F9/3013 , G06F9/3824 , G06F9/3838 , G06F9/384 , G06F9/3855
摘要： A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.
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公开(公告)号：US20070113214A1
公开(公告)日：2007-05-17
申请号：US11651467
申请日：2007-01-10
申请人： Kevin Iadonato , Le Nguyen
发明人： Kevin Iadonato , Le Nguyen
CPC分类号： G06F9/30141 , G06F9/3824 , G06F9/3826 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F17/5068
摘要： An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.
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公开(公告)号：US06772327B2
公开(公告)日：2004-08-03
申请号：US10143230
申请日：2002-05-09
IPC分类号： G06F938
CPC分类号： G06F9/3885 , G06F9/30149 , G06F9/3861
摘要： An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.
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