公开(公告)号：US20080059770A1

公开(公告)日：2008-03-06

申请号：US11730566

申请日：2007-04-02

申请人： Sanjiv Garg ,  Kevin Iadonato ,  Le Nguyen ,  Johannes Wang

发明人： Sanjiv Garg ,  Kevin Iadonato ,  Le Nguyen ,  Johannes Wang

IPC分类号： G06F9/312

CPC分类号： G06F9/3013 ,  G06F9/3824 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855

摘要： A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.

摘要翻译： 一种用于无序执行一组具有可寻址源和目的寄存器字段的精简指令集计算机指令的寄存器重命名系统，适用于具有指令执行单元的计算机，该指令执行单元具有通过读地址端口访问的寄存器文件， 存储指令操作数。 包括数据相关性检查电路，用于确定指令之间的数据依赖性。 标签分配电路基于由数据相关性检查电路确定的数据依赖性，生成一个或多个标签以指定操作数的位置。 一组寄存器文件端口复用器选择标签分配电路产生的标签，并将标签传递到寄存器文件的读取地址端口，以存储执行结果。

公开(公告)号：US20060041736A1

公开(公告)日：2006-02-23

申请号：US11252820

申请日：2005-10-19

申请人： Sanjiv Garg ,  Kevin Iadonato ,  Le Nguyen ,  Johannes Wang

发明人： Sanjiv Garg ,  Kevin Iadonato ,  Le Nguyen ,  Johannes Wang

IPC分类号： G06F15/76 ,  G06F15/00

CPC分类号： G06F9/3013 ,  G06F9/3824 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855

摘要： A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.

公开(公告)号：US20050283591A1

公开(公告)日：2005-12-22

申请号：US11113135

申请日：2005-04-25

申请人： Cheryl Brashears ,  Johannes Wang ,  Le Nguyen ,  Derek Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang Trang

发明人： Cheryl Brashears ,  Johannes Wang ,  Le Nguyen ,  Derek Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang Trang

IPC分类号： G06F9/00 ,  G06F9/312 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3017 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885

摘要： The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data.

公开(公告)号：US20070106878A1

公开(公告)日：2007-05-10

申请号：US11642599

申请日：2006-12-21

申请人： Le Nguyen ,  Derek Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang Trang

发明人： Le Nguyen ,  Derek Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang Trang

IPC分类号： G06F9/30

CPC分类号： G06F9/3822 ,  G06F9/30061 ,  G06F9/30072 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3885

摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

摘要翻译： 高性能，基于超标量的计算机系统，具有无序指令执行功能，可提高资源利用率和性能吞吐量。 计算机系统以指定的顺序程序顺序（按顺序）获取多个固定长度指令。 计算机系统包括指令执行单元，其包括寄存器文件，多个功能单元以及指令控制单元，用于检查指令并调度用于由功能单元执行无序执行的指令。 寄存器文件包括一组由指令执行控制单元用于接收由功能单元产生的数据结果的临时数据寄存器。 每个执行指令的数据结果存储在临时数据寄存器中，直到执行所有先前的指令为止，从而按顺序退出执行的指令。

公开(公告)号：US20060149925A1

公开(公告)日：2006-07-06

申请号：US11316814

申请日：2005-12-27

申请人： Le Nguyen ,  Derek Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang Trang

发明人： Le Nguyen ,  Derek Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang Trang

IPC分类号： G06F15/00

CPC分类号： G06F9/30167 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30141 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3865 ,  G06F9/3885

摘要： The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of instructions in an instruction buffer. The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations. A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available. Unified scheduling is performed across multiple execution data paths, where each execution data path, and corresponding functional units, is generally optimized for the type of computational function that is to be performed on the data: integer, floating point, and boolean. The number, type and computational specifics of the functional units provided in each data path, and as between data paths, are mutually independent.

公开(公告)号：US20070101103A1

公开(公告)日：2007-05-03

申请号：US11640967

申请日：2006-12-19

申请人： Le Nguyen ,  Derek Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang Trang

发明人： Le Nguyen ,  Derek Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang Trang

IPC分类号： G06F9/30

CPC分类号： G06F9/30167 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30141 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3865 ,  G06F9/3885

摘要： The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of instructions in an instruction buffer. The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations. A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available. Unified scheduling is performed across multiple execution data paths, where each execution data path, and corresponding functional units, is generally optimized for the type of computational function that is to be performed on the data: integer, floating point, and boolean. The number, type and computational specifics of the functional units provided in each data path, and as between data paths, are mutually independent.

摘要翻译： 高性能的基于RISC核心的微处理器架构包括用于从指令存储器取出指令集的指令获取单元和通过并行的功能单元阵列实现多个指令的并发执行的执行单元。 提取单元通常在指令缓冲器中保持预定数量的指令。 执行单元包括指令选择单元，耦合到指令缓冲器，用于选择用于执行的指令;以及多个功能单元，用于执行指令指定的功能操作。 在指令选择单元内的统一指令调度器，当确定可用于执行的指令并且实现必要的计算功能的功能单元中的至少一个可用时，通过功能单元启动对指令的处理。 在多个执行数据路径上执行统一调度，其中每个执行数据路径和相应的功能单元通常针对要在数据上执行的计算函数类型进行优化：整数，浮点和布尔值。 在每个数据路径中以及数据路径之间提供的功能单元的数量，类型和计算细节是相互独立的。

公开(公告)号：US07516305B2

公开(公告)日：2009-04-07

申请号：US11642625

申请日：2006-12-21

申请人： Johannes Wang ,  Sanjiv Garg ,  Trevor Deosaran

发明人： Johannes Wang ,  Sanjiv Garg ,  Trevor Deosaran

IPC分类号： G06F9/30

CPC分类号： G06F9/3012 ,  G06F9/3013 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3885

摘要： An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results. In addition, the retirement control block further controls the retiring of a group of instructions determined to be retirable, by simultaneously transferring their results from the temporary buffer to the register array, and retires instructions executed in order by storing their results directly in the register array. The method comprises the steps of monitoring the status of the instructions to determine which group of instructions have been executed, determining whether each executed instruction is retirable, storing results of instructions executed out of program order in a temporary buffer, storing retirable-instruction results in a register array and retiring a group of retirable instructions by simultaneously transferring their results from the temporary buffer to the register array, and retiring instructions executed in order by storing their results directly in the register array.

公开(公告)号：US20090013155A1

公开(公告)日：2009-01-08

申请号：US12212361

申请日：2008-09-17

申请人： Johannes Wang ,  Sanjiv Garg ,  Trevor Deosaran

发明人： Johannes Wang ,  Sanjiv Garg ,  Trevor Deosaran

IPC分类号： G06F9/30

CPC分类号： G06F9/3012 ,  G06F9/3013 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3885

摘要： An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results. In addition, the retirement control block further controls the retiring of a group of instructions determined to be retirable, by simultaneously transferring their results from the temporary buffer to the register array, and retires instructions executed in order by storing their results directly in the register array. The method comprises the steps of monitoring the status of the instructions to determine which group of instructions have been executed, determining whether each executed instruction is retirable, storing results of instructions executed out of program order in a temporary buffer, storing retirable-instruction results in a register array and retiring a group of retirable instructions by simultaneously transferring their results from the temporary buffer to the register array, and retiring instructions executed in order by storing their results directly in the register array.

摘要翻译： 一种用于在超标量微处理器中停止指令的系统和方法，该系统和方法执行包括具有预定程序顺序的一组指令的程序，所述退出系统用于同时停止由微处理器执行或不按顺序执行的指令组。 退休系统包括：完成块，用于监视指令的状态以确定已经执行了哪个指令或指令组，用于确定每个执行的指令是否可取回的退出控制块;用于存储执行的指令结果的临时缓冲器 程序顺序和用于存储可取样指令结果的寄存器阵列。 此外，退休控制块还通过将其结果从临时缓冲器同时传送到寄存器阵列来进一步控制确定为可延展的一组指令的退役，并且通过将其结果直接存储在寄存器阵列中来依次执行的指令 。 该方法包括以下步骤：监视指令的状态以确定已经执行了哪组指令，确定每个被执行的指令是否可以被取消，将在程序顺序中执行的指令的结果存储在临时缓冲器中，存储可检索指令结果 一个寄存器阵列，并通过将它们的结果从临时缓冲器同时传送到寄存器阵列，并且将其结果直接存储在寄存器阵列中，按顺序执行退出指令，并退出一组可重试指令。

公开(公告)号：US07051187B2

公开(公告)日：2006-05-23

申请号：US10086197

申请日：2002-03-01

申请人： Sanjiv Garg ,  Kevin Ray Iadonato ,  Le Trong Nguyen ,  Johannes Wang

发明人： Sanjiv Garg ,  Kevin Ray Iadonato ,  Le Trong Nguyen ,  Johannes Wang

IPC分类号： G06F9/38

CPC分类号： G06F9/3013 ,  G06F9/3824 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855

摘要： A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.

公开(公告)号：US06959375B2

公开(公告)日：2005-10-25

申请号：US10282045

申请日：2002-10-29

申请人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

发明人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

IPC分类号： G06F9/32 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F9/42 ,  G06F9/50 ,  G06F15/16

CPC分类号： G06F9/3822 ,  G06F9/30061 ,  G06F9/30072 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3885

摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

摘要翻译： 高性能，基于超标量的计算机系统，具有无序指令执行功能，可提高资源利用率和性能吞吐量。 计算机系统以指定的顺序程序顺序（按顺序）获取多个固定长度指令。 计算机系统包括指令执行单元，其包括寄存器文件，多个功能单元以及指令控制单元，用于检查指令并调度用于由功能单元执行无序执行的指令。 寄存器文件包括一组由指令执行控制单元用于接收由功能单元产生的数据结果的临时数据寄存器。 每个执行指令的数据结果存储在临时数据寄存器中，直到执行所有先前的指令为止，从而按顺序退出执行的指令。