Gate etch process
    1.
    发明授权
    Gate etch process 有权
    门蚀刻工艺

    公开(公告)号:US06699795B1

    公开(公告)日:2004-03-02

    申请号:US10099841

    申请日:2002-03-15

    IPC分类号: H01L21302

    摘要: A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a second nitride etch plasma having a second F:C ratio. The first F:C ratio is greater than the second F:C ratio.

    摘要翻译: 制造半导体结构的方法包括在10毫托或更低的压力下蚀刻抗反射涂层; 用具有第一F:C比率的第一氮化物蚀刻等离子体蚀刻氮化物层; 并用具有第二F:C比率的第二氮化物蚀刻等离子体蚀刻氮化物层。 第一F:C比大于第二F:C比。

    Gate etch process
    2.
    发明授权
    Gate etch process 有权
    门蚀刻工艺

    公开(公告)号:US07112834B1

    公开(公告)日:2006-09-26

    申请号:US10791657

    申请日:2004-03-02

    IPC分类号: H01L29/76

    摘要: A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a second nitride etch plasma having a second F:C ratio. The first F:C ratio is greater than the second F:C ratio.

    摘要翻译: 制造半导体结构的方法包括在10毫托或更低的压力下蚀刻抗反射涂层; 用具有第一F:C比率的第一氮化物蚀刻等离子体蚀刻氮化物层; 并用具有第二F:C比率的第二氮化物蚀刻等离子体蚀刻氮化物层。 第一F:C比大于第二F:C比。