Gate etch process
    1.
    发明授权
    Gate etch process 有权
    门蚀刻工艺

    公开(公告)号:US07112834B1

    公开(公告)日:2006-09-26

    申请号:US10791657

    申请日:2004-03-02

    IPC分类号: H01L29/76

    摘要: A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a second nitride etch plasma having a second F:C ratio. The first F:C ratio is greater than the second F:C ratio.

    摘要翻译: 制造半导体结构的方法包括在10毫托或更低的压力下蚀刻抗反射涂层; 用具有第一F:C比率的第一氮化物蚀刻等离子体蚀刻氮化物层; 并用具有第二F:C比率的第二氮化物蚀刻等离子体蚀刻氮化物层。 第一F:C比大于第二F:C比。

    Gate etch process
    2.
    发明授权
    Gate etch process 有权
    门蚀刻工艺

    公开(公告)号:US06699795B1

    公开(公告)日:2004-03-02

    申请号:US10099841

    申请日:2002-03-15

    IPC分类号: H01L21302

    摘要: A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a second nitride etch plasma having a second F:C ratio. The first F:C ratio is greater than the second F:C ratio.

    摘要翻译: 制造半导体结构的方法包括在10毫托或更低的压力下蚀刻抗反射涂层; 用具有第一F:C比率的第一氮化物蚀刻等离子体蚀刻氮化物层; 并用具有第二F:C比率的第二氮化物蚀刻等离子体蚀刻氮化物层。 第一F:C比大于第二F:C比。

    SEMICONDUCTOR PROCESS
    10.
    发明申请
    SEMICONDUCTOR PROCESS 有权
    半导体工艺

    公开(公告)号:US20130137243A1

    公开(公告)日:2013-05-30

    申请号:US13308513

    申请日:2011-11-30

    IPC分类号: H01L21/20

    摘要: First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below −30° C.

    摘要翻译: 首先,在半导体工艺中设置具有凹部的基板。 第二,在衬底中形成嵌入的SiGe层。 嵌入的SiGe层包括填充凹槽的外延SiGe材料。 然后,在嵌入的SiGe层上进行预非晶化植入(PAI)工艺以形成非晶区域。 接下来,在嵌入的SiGe层上进行源极/漏极注入工艺以形成源极掺杂区域和漏极掺杂区域。 之后,进行源极/漏极退火处理以在衬底中形成源极和漏极。 前非晶化植入程序和源极/漏极注入程序中的至少一个在低于-30℃的低温过程中进行。