公开(公告)号：US06259293B1

公开(公告)日：2001-07-10

申请号：US09413528

申请日：1999-10-06

申请人： Kiyoshi Hayase ,  Kouichi Ishimi

发明人： Kiyoshi Hayase ,  Kouichi Ishimi

IPC分类号： H03H1126

CPC分类号： H03L7/0805 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00032 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0995

摘要： Delay circuitry includes a phase-locked loop or PLL for comparing the phase of a reference clock applied thereto with that of another clock to be compared to generate a control signal having a value corresponding to the phase difference between the phases of the reference clock and other clock, for generating the other clock using at least a plurality of delay elements connected into a loop, a time delay provided by each of the plurality of delay elements being controlled by the control signal, and for changing the value of the control signal so that the other clock is made to be in phase with the reference clock. The delay circuitry further includes a register for storing information to set a certain time delay, and a delay unit including a plurality of delay elements each of which provides an input with a time delay that is controlled by the control signal from the PLL, for determining the number of delay elements through which an input signal is to be passed according to the information stored in the register, so as to provide the input signal with the predetermined time delay.

摘要翻译： 延迟电路包括锁相环或PLL，用于将施加到其上的参考时钟的相位与要比较的另一个时钟的相位相比较，以产生具有对应于参考时钟和其它相位的相位之间的相位差的值的控制信号 时钟，用于使用连接到一个环路中的至少多个延迟元件产生另一个时钟，由所述多个延迟元件中的每一个提供的时间延迟由所述控制信号控制，并且用于改变所述控制信号的值，使得 另一个时钟与参考时钟同相。 所述延迟电路还包括用于存储用于设定一定时间延迟的信息的寄存器，以及包括多个延迟元件的延迟单元，每个延迟元件为由输入端提供来自PLL的控制信号控制的时间延迟输入，以确定 根据存储在寄存器中的信息通过其输入输入信号的延迟元件的数量，以便为输入信号提供预定的时间延迟。