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公开(公告)号：US07392273B2
公开(公告)日：2008-06-24
申请号：US10732039
申请日：2003-12-10
CPC分类号： G06F7/483 , G06F5/012 , G06F7/5443
摘要： Arithmetic processing circuits in a circuit in a floating point processor having a fused multiply/ADD circuitry. In order to avoid waiting cycles in the normalizer of the floating point arithmetic, control logic calculates in an extremely early state of the overall Multiply/Add processing. Parts of the intermediate add result are significant and have to be selected in the pre-normalizer multiplexer to be fed to the normalizer by counting the leading zero bits (LAB) of the addend in a dedicated circuit right at the beginning of the pipe. LAB is added to the shift amount (SA) that is calculated to align the addend and is then compared with the width of the incrementer. If the sum of (SA+LAB) is larger than the width of the incrementer, which is a constant value, then no significant bits are in the high-part of the intermediate result, and the pre-normalizer multiplexer selects the data from a second predetermined position, otherwise from a first predetermined position.
摘要翻译： 具有融合乘法/ ADD电路的浮点处理器中的电路中的算术处理电路。 为了避免浮点运算的归一化器中的等待周期，控制逻辑在整体乘法/加法处理的极早期状态下进行计算。 中间加法结果的部分是重要的，必须在预归一化器多路复用器中选择，以通过在管道开头右侧的专用电路中的加数的前导零比特（LAB）进行计数来馈送到归一化器。 将LAB加到被计算以对齐加数的移位量（SA），然后与增量器的宽度进行比较。 如果（SA + LAB）的和大于作为常数值的增量器的宽度，则中间结果的高部分中没有有效位，并且预标准化器多路复用器选择来自 第二预定位置，否则从第一预定位置。
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2.发明授权Floating point unit with fused multiply add and method for calculating a result with a floating point unit 失效具有融合乘法的浮点单元和用浮点单元计算结果的方法公开(公告)号：US07461117B2
公开(公告)日：2008-12-02
申请号：US11055812
申请日：2005-02-11
申请人： Son Dao Trong , Juergen Haess , Christian Jacobi , Klaus Michael Kroener , Silvia Melitta Mueller , Jochen Preiss
发明人： Son Dao Trong , Juergen Haess , Christian Jacobi , Klaus Michael Kroener , Silvia Melitta Mueller , Jochen Preiss
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/5443
摘要： The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with an alignment logic (3) which uses the alignment shift amount to align the fraction (fb) of the addend operand, with a multiply logic (4) which multiplies the fractions of the multiplicand operands (fa, fc), with a adder logic (5) which adds the outputs of the alignment logic (3) and the multiply logic (4), with a normalization logic (6) which normalizes the output of the adder logic (5), which is characterized in that a leading zero logic (7) is provided which computes the number of leading zeros of the fraction of the addend operand (fb), and that a compare logic (8) is provided which based on the number of leading zeros and the alignment shift amount computes select signals that indicate whether the most significant bits of the alignment logic (3) output have all the same value in order to: a) control the carry logic of the adder logic (5) and/or b) control a stage of the normalization logic (6).
摘要翻译： 本发明提出了一种具有融合乘法运算的浮点单元（1），具有一个加数运算数（eb，fb）和两个被乘数运算符（ea，fa; ec，fc），其中移位量逻辑（2）基于 操作数（ea，eb和ec）的指数利用对准逻辑（3）计算对准偏移量，该对准逻辑（3）使用对准移位量来对齐加数操作数的分数（fb）与乘法逻辑（4） 将乘法器操作数（fa，fc）的分数与加法器逻辑（5）相乘，该逻辑（5）将对准逻辑（3）和乘法逻辑（4）的输出与归一化逻辑（6）进行归一化，归一化逻辑（6） 加法器逻辑（5）的特征在于提供一个前导零逻辑（7），其计算加法运算数（fb）的分数的前导零的数量，并且提供比较逻辑（8） 其基于前导零的数量和对准偏移量计算指示mo的选择信号 对准逻辑（3）输出的高有效位具有全部相同的值，以便：a）控制加法器逻辑（5）的进位逻辑和/或b）控制归一化逻辑（6）的阶段。
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公开(公告)号：US07716266B2
公开(公告)日：2010-05-11
申请号：US11341256
申请日：2006-01-26
CPC分类号： G06F7/483 , G06F7/5443 , G06F2207/3812
摘要： A method and system for performing a binary mode and hexadecimal mode Multiply-Add floating point operation in a floating point arithmetic unit according to a formula A*C+B, wherein A, B and C operands each have a fraction and an exponent part expA, expB and expC and the exponent of the product A*C is calculated and compared to the exponent of the addend under inclusion of an exponent bias value dedicated to use unsigned biased exponents, wherein the comparison yields a shift amount used for aligning the addend with the product operand, wherein a shift amount calculation provides a common value CV for both binary and hexadecimal according to the formula (expA+expC−expB+CV).
摘要翻译： 一种用于执行二进制模式和十六进制模式的方法和系统根据公式A * C + B在浮点算术单元中乘法 - 浮点运算，其中A，B和C操作数各自具有分数和指数部分expA ，expB和expC和乘积A * C的指数被计算，并且与包含专用于使用无符号偏移指数的指数偏差值的加数指数进行比较，其中比较产生用于将加数与 产品操作数，其中移位量计算根据公式（expA + expC-expB + CV）为二进制和十六进制提供公共值CV。
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公开(公告)号：US06694344B1
公开(公告)日：2004-02-17
申请号：US09436851
申请日：1999-11-09
申请人： Guenter Gerwig , Juergen Haess , Michael Kroener , Erwin Pfeffer
发明人： Guenter Gerwig , Juergen Haess , Michael Kroener , Erwin Pfeffer
IPC分类号： G06F1100
CPC分类号： G06F11/085 , G06F7/72 , H03M7/02
摘要： A process is provided for monitoring the conversion of numerical values from a first to a second format, where before and after the conversion, the modulo residue of the corresponding numerical value is calculated and compared with the corresponding residue after the conversion. In this way it is possible to effect error-free monitoring of such a conversion, especially of computer data, without great hardware expenditure.
摘要翻译： 提供了用于监视从第一格式到第二格式的数值的转换的过程，其中在转换之前和之后，计算相应数值的模余数并将其与转换后的相应残差进行比较。 以这种方式，可以在没有很好的硬件支出的情况下，对这种转换，特别是计算机数据进行无差错监视。
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公开(公告)号：US08892958B2
公开(公告)日：2014-11-18
申请号：US13525054
申请日：2012-06-15
IPC分类号： G06F11/00
CPC分类号： G06F11/3476 , G06F11/34 , G06F11/348 , G06F11/3636
摘要： In a data processing system a plurality of signals associated with an operation are received during execution of the operation. In response to an indication that the operation is a multiphase operation, during execution of the operation, selection logic, during a first phase of the multiphase operation, selects and outputs as a trace signal a first signal of the plurality of signals, and during a second phase of the multiphase operation, selects and outputs as the trace signal a second signal of the plurality of signals.
摘要翻译： 在数据处理系统中，在执行操作期间接收与操作相关联的多个信号。 响应于操作是多相操作的指示，在执行操作期间，选择逻辑在多相操作的第一阶段期间，选择并输出多个信号的第一信号作为跟踪信号，并且在 多相操作的第二相，选择并输出多个信号的第二信号作为迹线信号。
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6.发明申请RESIDUE-BASED ERROR DETECTION FOR A PROCESSOR EXECUTION UNIT THAT SUPPORTS VECTOR OPERATIONS 有权支持向导操作的处理器执行单元的基于残差的错误检测公开(公告)号：US20130204916A1
公开(公告)日：2013-08-08
申请号：US13367032
申请日：2012-02-06
申请人： Maarten Boersma , Juergen Haess
发明人： Maarten Boersma , Juergen Haess
IPC分类号： G06F7/38
CPC分类号： G06F7/38 , G06F7/483 , G06F7/5443 , G06F7/72 , G06F11/1008
摘要： A residue generating circuit for an execution unit that supports vector operations includes an operand register and a residue generator coupled to the operand register. The residue generator includes a first residue generation tree coupled to a first section of the operand register and a second residue generation tree coupled to a second section of the operand register. The first residue generation tree is configured to generate a first residue for first data included in the first section of the operand register. The second residue generation tree is configured to generate a second residue for second data included in a second section of the operand register. The first section of the operand register includes a different number of register bits than the second section of the operand register. Configuring a residue-generation tree to be split into multiple residue generation trees facilitates residue checking multiple independent vector instruction operands within a full width dataflow in parallel or alternatively residue checking a full width operand of a standard instruction.
摘要翻译： 用于支持向量操作的执行单元的残差产生电路包括耦合到操作数寄存器的操作数寄存器和残差发生器。 残余生成器包括耦合到操作数寄存器的第一部分的第一残余生成树和耦合到操作数寄存器的第二部分的第二残留生成树。 第一残差生成树被配置为为包括在操作数寄存器的第一部分中的第一数据产生第一残余。 第二残差产生树被配置为产生包括在操作数寄存器的第二部分中的第二数据的第二残差。 操作数寄存器的第一部分包括与操作数寄存器的第二部分不同的寄存器位数。 配置要分割为多个残差生成树的残留生成树有助于在全宽数据流内并行检查多个独立向量指令操作数，或者替代残差检查标准指令的全宽操作数。
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7.发明授权Residue-based error detection for a processor execution unit that supports vector operations 有权用于支持向量操作的处理器执行单元的基于残差的错误检测公开(公告)号：US08984039B2
公开(公告)日：2015-03-17
申请号：US13367032
申请日：2012-02-06
CPC分类号： G06F7/38 , G06F7/483 , G06F7/5443 , G06F7/72 , G06F11/1008
摘要： A residue generating circuit for an execution unit that supports vector operations includes an operand register and a residue generator coupled to the operand register. The residue generator includes a first residue generation tree coupled to a first section of the operand register and a second residue generation tree coupled to a second section of the operand register. The first residue generation tree is configured to generate a first residue for first data included in the first section of the operand register. The second residue generation tree is configured to generate a second residue for second data included in a second section of the operand register. The first section of the operand register includes a different number of register bits than the second section of the operand register.
摘要翻译： 用于支持向量操作的执行单元的残差产生电路包括耦合到操作数寄存器的操作数寄存器和残差发生器。 残余生成器包括耦合到操作数寄存器的第一部分的第一残余生成树和耦合到操作数寄存器的第二部分的第二残留生成树。 第一残差生成树被配置为为包括在操作数寄存器的第一部分中的第一数据产生第一残余。 第二残差产生树被配置为产生包括在操作数寄存器的第二部分中的第二数据的第二残差。 操作数寄存器的第一部分包括与操作数寄存器的第二部分不同的寄存器位数。
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公开(公告)号：US07085865B2
公开(公告)日：2006-08-01
申请号：US10895654
申请日：2004-07-21
申请人： Juergen Haess , Ingemar Holm , Hartmut Ulland , Gerhard Zilles
发明人： Juergen Haess , Ingemar Holm , Hartmut Ulland , Gerhard Zilles
CPC分类号： G06F13/364
摘要： The invention provides a method of transmitting data via a bus system coupling a plurality of bus participants with an arbitration procedure for the plurality of bus participants. The invention further enables bus arbitration during a first transmission since that the bus can be granted for a second transmission following the first transmission without wasting bus cycles. This is accomplished by determining the number of cycles remaining for the first transmission according to memory boundary and transmission packet boundary conditions.
摘要翻译： 本发明提供了一种经由总线系统发送数据的方法，该总线系统将多个总线参与者与多个总线参与者的仲裁程序相结合。 本发明还允许在第一次传输期间的总线仲裁，因为总线可以在第一次传输之后被授权用于第二次传输，而不浪费总线周期。 这是通过根据存储器边界和传输分组边界条件确定第一次传输剩余的周期数来实现的。
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9.发明申请Floating point unit with fused multiply add and method for calculating a result with a floating point unit 失效具有融合乘法的浮点单元和用浮点单元计算结果的方法公开(公告)号：US20060184601A1
公开(公告)日：2006-08-17
申请号：US11055812
申请日：2005-02-11
申请人： Son Trong , Juergen Haess , Christian Jacobi , Klaus Kroener , Silvia Mueller , Jochen Preiss
发明人： Son Trong , Juergen Haess , Christian Jacobi , Klaus Kroener , Silvia Mueller , Jochen Preiss
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/5443
摘要： The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with an alignment logic (3) which uses the alignment shift amount to align the fraction (fb) of the addend operand, with a multiply logic (4) which multiplies the fractions of the multiplicand operands (fa, fc), with a adder logic (5) which adds the outputs of the alignment logic (3) and the multiply logic (4), with a normalization logic (6) which normalizes the output of the adder logic (5), which is characterized in that a leading zero logic (7) is provided which computes the number of leading zeros of the fraction of the addend operand (fb), and that a compare logic (8) is provided which based on the number of leading zeros and the alignment shift amount computes select signals that indicate whether the most significant bits of the alignment logic (3) output have all the same value in order to: a) control the carry logic of the adder logic (5) and/or b) control a stage of the normalization logic (6).
摘要翻译： 本发明提出了一种具有融合乘法运算的浮点单元（1），具有一个加数运算数（eb，fb）和两个被乘数运算符（ea，fa; ec，fc），其中移位量逻辑（2）基于 操作数（ea，eb和ec）的指数利用对准逻辑（3）计算对准偏移量，该对准逻辑（3）使用对准移位量来对齐加数操作数的分数（fb）与乘法逻辑（4） 将乘法器操作数（fa，fc）的分数与加法器逻辑（5）相乘，该逻辑（5）将对准逻辑（3）和乘法逻辑（4）的输出与归一化逻辑（6）进行归一化，归一化逻辑（6） 加法器逻辑（5）的特征在于提供一个前导零逻辑（7），其计算加法运算数（fb）的分数的前导零的数量，并且提供比较逻辑（8） 其基于前导零的数量和对准移位量计算选择信号i 指出对齐逻辑（3）输出的最高有效位是否具有全部相同的值，以便：a）控制加法器逻辑（5）的进位逻辑和/或b）控制归一化逻辑（6 ）。
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公开(公告)号：US20060179100A1
公开(公告)日：2006-08-10
申请号：US11054686
申请日：2005-02-09
申请人： Juergen Haess , Michael Kroener , Dung Nguyen , Lawrence Powell , Eric Schwarz , Son Dao-Trong , Raymond Yeung
发明人： Juergen Haess , Michael Kroener , Dung Nguyen , Lawrence Powell , Eric Schwarz , Son Dao-Trong , Raymond Yeung
IPC分类号： G06F7/38
CPC分类号： G06F9/3826 , G06F9/30014 , G06F9/3824 , G06F9/3838 , G06F9/3885
摘要： A system for performing floating point arithmetic operations including a plurality of stages making up a pipeline, the stages including a first stage and a last stage. The system also includes a register file adapted for receiving a store instruction for input to the pipeline, where the data associated with the store instruction is dependent on a previous operation still in the pipeline. The system further includes a store register adapted for outputting the data associated with the store instruction to memory and a control unit having instructions. The instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the last stage in the pipeline to the store register for use by the store instruction if the previous operation immediately precedes the store operation in the pipeline and if there is a data type match between the store instruction and the previous operation. In addition, the instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the first stage in the pipeline to the store register for use by the store instruction if the previous operation precedes the store operation by one or more stage in the pipeline and if there is a data type match between the store instruction and the previous operation.
摘要翻译： 一种用于执行浮点算术运算的系统，包括构成流水线的多个级，所述级包括第一级和最后级。 该系统还包括适于接收用于输入到流水线的存储指令的寄存器文件，其中与存储指令相关联的数据依赖于仍在流水线中的先前操作。 该系统还包括适于将与存储指令相关联的数据输出到存储器的存储寄存器和具有指令的控制单元。 这些指令旨在将存储指令输入到流水线中，并且提供一个路径，用于将与流水线中的最后一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用，如果先前的操作紧接在 存储操作在流水线中，并且存储指令与先前操作之间存在数据类型匹配。 此外，该指令旨在将存储指令输入到流水线中，并且提供用于将与流水线中的第一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用的路径，如果先前的操作 在存储操作之前在流水线中的一个或多个阶段，以及存储指令和先前操作之间是否存在数据类型匹配。
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