公开(公告)号：US20160068418A1

公开(公告)日：2016-03-10

申请号：US14482940

申请日：2014-09-10

申请人： Ku-Fan Chen ,  Kuan-Yu Liu ,  Yu-Chen Chang

发明人： Ku-Fan Chen ,  Kuan-Yu Liu ,  Yu-Chen Chang

IPC分类号： C02F1/72 ,  C02F1/68

CPC分类号： C02F1/722 ,  C02F2101/20 ,  C02F2101/36 ,  C02F2103/06 ,  C02F2103/34 ,  C02F2209/06

摘要： A method for raising pH value to enhance degradation of chlorinated organics by oxidation may include steps of adding 1% persulfate and 20-100 g slag to 50 mg/L chlorinated organics; and utilizing slag to increase the pH to 12-13, and make persulfate alkali-activated to enhance the degradation of chlorinated organics and prevent heavy metal pollute the soil.

摘要翻译： 提高pH值以提高氯化有机物通过氧化降解的方法可包括向50mg / L氯化有机物中加入1％过硫酸盐和20-100g渣的步骤; 利用炉渣将pH值提高到12-13，并使过硫酸碱被活化，提高氯化有机物的降解，防止重金属污染土壤。

公开(公告)号：US07944750B1

公开(公告)日：2011-05-17

申请号：US12288762

申请日：2008-10-22

申请人： Albert Bergemont ,  David Kuan-Yu Liu ,  Venkatraman Prabhakar ,  Sridevi Rajagopalan Schmidt

发明人： Albert Bergemont ,  David Kuan-Yu Liu ,  Venkatraman Prabhakar ,  Sridevi Rajagopalan Schmidt

IPC分类号： G11C16/04

CPC分类号： G11C16/0408 ,  G11C16/10

摘要： A non-volatile memory device and method for manufacture and programing which does not require a control gate for the programing or erasure of the device. The memory device is comprised of two wells with the opposite conductivity type of the semiconductor body. In one of the wells is a source and drain well of the same conductivity type as of the body. A oxide is formed on the surface of the body on which a floating gate is formed. Specific voltages are applied to the source, drain, first well and second well region to program, erase and read the memory device.

摘要翻译： 用于制造和编程的非易失性存储器件和方法，其不需要用于编程或擦除器件的控制栅极。 存储器件由具有相反导电类型的半导体本体的两个阱构成。 其中一个井是与身体相同的导电类型的源极和漏极井。 在其上形成有浮动栅极的主体的表面上形成氧化物。 将特定电压施加到源极，漏极，第一阱和第二阱区域以对存储器件进行编程，擦除和读取。

公开(公告)号：US07535758B2

公开(公告)日：2009-05-19

申请号：US11703922

申请日：2007-02-06

申请人： Albert Bergemont ,  David Kuan-Yu Liu ,  Venkatraman Prabhakar

发明人： Albert Bergemont ,  David Kuan-Yu Liu ,  Venkatraman Prabhakar

IPC分类号： G11C16/04

CPC分类号： H01L29/7885 ,  G11C16/0416 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： Methods and apparatus, including computer program products, for a one or multiple-times programmable memory device. A semiconductor may include an active region of a substrate, a thin oxide layer over a substrate, a first and second polysilicon layer, and a first and second metal layer. The first polysilicon layer may have a floating gate, the active region may be substantially perpendicular to the floating gate, and the second polysilicon layer may include a control gate. The first metal layer may include a bit line connected to a first n-diffused region, where the bit line is substantially perpendicular to the floating gate. The second metal layer may include a word line and source line. The word line may be connected to the control gate, and the source line may be connected to a second n-diffused region. The thin gate oxide may have a thickness between 65 and 75 angstroms.

摘要翻译： 用于一次或多次可编程存储器件的方法和装置，包括计算机程序产品。 半导体可以包括衬底的有源区，衬底上的薄氧化层，第一和第二多晶硅层以及第一和第二金属层。 第一多晶硅层可以具有浮置栅极，有源区可以基本上垂直于浮置栅极，并且第二多晶硅层可以包括控制栅极。 第一金属层可以包括连接到第一n扩散区域的位线，其中位线基本上垂直于浮动栅极。 第二金属层可以包括字线和源极线。 字线可以连接到控制栅极，并且源极线可以连接到第二n扩散区域。 薄栅氧化物可以具有65和75埃之间的厚度。

公开(公告)号：US20080273401A1

公开(公告)日：2008-11-06

申请号：US12168863

申请日：2008-07-07

申请人： Nirmal Ratnakumar ,  Venkatraman Prabhakar ,  David Kuan-Yu Liu

发明人： Nirmal Ratnakumar ,  Venkatraman Prabhakar ,  David Kuan-Yu Liu

IPC分类号： G11C16/16

CPC分类号： G11C16/0441 ,  G11C16/3427 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

摘要： A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell.

摘要翻译： 一种包括多个存储单元的存储器件，每个存储器单元具有与编程/擦除PMOS晶体管共享浮置栅极的控制栅极NMOS晶体管，该晶体管又与访问PMOS晶体管串联连接。 存储单元形成在形成在P基板中的公共N阱中，NMOS晶体管形成在p掺杂的凹穴或基底中。 编程/擦除PMOS包括栅极和形成在N阱中的第一和第二P +掺杂区域，其中第一P +区域电连接到相应的位线。 存取PMOS包括栅极和形成在N阱内的第一和第二P +区，其中第一P +区电连接到编程/擦除PMOS的第二P +区，并且栅极电连接到相应的字 线。 控制栅极NMOS包括源极，漏极和栅极，其中源极和第三漏极以及p掺杂的阱电连接到相应的控制栅极线，并且栅极电连接到编程/擦除的栅极 PMOS，形成电池的浮动栅极。

公开(公告)号：US20100184385A1

公开(公告)日：2010-07-22

申请号：US12403630

申请日：2009-03-13

申请人： Yung-Da Lin ,  Sheng-Cheng Chang ,  Yu-Hsiang Chen ,  Kuan-Yu Liu

发明人： Yung-Da Lin ,  Sheng-Cheng Chang ,  Yu-Hsiang Chen ,  Kuan-Yu Liu

IPC分类号： H04B1/38

CPC分类号： H04N7/20 ,  H04H40/90 ,  H04N21/4143 ,  H04N21/6143

摘要： A data communication system and a data communication method are provided. The data communication system comprises a bidirectional cable, an antenna, a receiving and a function circuit block. The bidirectional cable transfers data through a high and a low frequency band. The antenna is to receive and transfer the analog data signal through the high frequency band of the bidirectional cable. The receiving circuit block comprises a receiving module to receive the analog data signal from the high frequency band and converts the analog data signal into a digital data to a host and a first control signal processing module to couple a control signal to the low frequency band. The function circuit block comprises a second control signal processing module to decouple the control signal from the low frequency band and a function module to perform an adjustment on the data communication system according to the control signal.

摘要翻译： 提供了数据通信系统和数据通信方法。 数据通信系统包括双向电缆，天线，接收和功能电路块。 双向电缆通过高频和低频带传输数据。 天线将通过双向电缆的高频段接收和传输模拟数据信号。 接收电路块包括接收模块，用于从高频带接收模拟数据信号，并将模拟数据信号转换成数字数据到主机和第一控制信号处理模块，以将控制信号耦合到低频带。 功能电路块包括用于使控制信号与低频带分离的第二控制信号处理模块和根据控制信号在数据通信系统上进行调整的功能模块。

公开(公告)号：US20090014772A1

公开(公告)日：2009-01-15

申请号：US12233294

申请日：2008-09-18

申请人： Nirmal Ratnakumar ,  Venkatraman Prabhakar ,  David Kuan-Yu Liu

发明人： Nirmal Ratnakumar ,  Venkatraman Prabhakar ,  David Kuan-Yu Liu

IPC分类号： H01L29/788

CPC分类号： G11C16/0441 ,  G11C16/3427 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

摘要： A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell.

摘要翻译： 一种包括多个存储单元的存储器件，每个存储器单元具有与编程/擦除PMOS晶体管共享浮置栅极的控制栅极NMOS晶体管，该晶体管又与访问PMOS晶体管串联连接。 存储单元形成在形成在P基板中的公共N阱中，NMOS晶体管形成在p掺杂的凹穴或基底中。 编程/擦除PMOS包括栅极和形成在N阱中的第一和第二P +掺杂区域，其中第一P +区域电连接到相应的位线。 存取PMOS包括栅极和形成在N阱内的第一和第二P +区，其中第一P +区电连接到编程/擦除PMOS的第二P +区，栅极电连接到相应的字 线。 控制栅极NMOS包括源极，漏极和栅极，其中源极和第三漏极以及p掺杂的阱电连接到相应的控制栅极线，并且栅极电连接到编程/擦除的栅极 PMOS，形成电池的浮动栅极。

公开(公告)号：US20080273392A1

公开(公告)日：2008-11-06

申请号：US12168858

申请日：2008-07-07

申请人： Nirmal Ratnakumar ,  Venkatraman Prabhakar ,  David Kuan-Yu Liu

发明人： Nirmal Ratnakumar ,  Venkatraman Prabhakar ,  David Kuan-Yu Liu

IPC分类号： G11C16/06

CPC分类号： G11C16/0441 ,  G11C16/3427 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

摘要： A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell.

摘要翻译： 一种包括多个存储单元的存储器件，每个存储器单元具有与编程/擦除PMOS晶体管共享浮置栅极的控制栅极NMOS晶体管，该晶体管又与访问PMOS晶体管串联连接。 存储单元形成在形成在P基板中的公共N阱中，NMOS晶体管形成在p掺杂的凹穴或基底中。 编程/擦除PMOS包括栅极和形成在N阱中的第一和第二P +掺杂区域，其中第一P +区域电连接到相应的位线。 存取PMOS包括栅极和形成在N阱内的第一和第二P +区，其中第一P +区电连接到编程/擦除PMOS的第二P +区，栅极电连接到相应的字 线。 控制栅极NMOS包括源极，漏极和栅极，其中源极和第三漏极以及p掺杂的阱电连接到相应的控制栅极线，并且栅极电连接到编程/擦除的栅极 PMOS，形成电池的浮动栅极。

公开(公告)号：US07091077B1

公开(公告)日：2006-08-15

申请号：US11146514

申请日：2005-06-07

申请人： David Kuan-Yu Liu ,  Jonathan Cheang-Whang Chang

发明人： David Kuan-Yu Liu ,  Jonathan Cheang-Whang Chang

IPC分类号： H01L21/336

CPC分类号： H01L21/28123 ,  H01L21/28035

摘要： Polysilicon or other material is directionally trimmed using two layers of photoresist and a photoresist etching process, such as ashing. A first layer of photoresist is patterned on a wafer. Portions of the first patterned photoresist are covered with a second layer of photoresist. The photoresist is trimmed to reduce the size of the exposed portions of the first patterned photoresist without reducing the size of the covered portions of the first patterned photoresist. The second layer of photoresist is removed. The selectively etched patterned first layer of photoresist is used as a process mask to define a structure in the underlying material. In a particular embodiment, the second photoresist covers endcap portions of gate photoresist. Directional trimming reduces the width of a polysilicon gate structure (i.e. gate length) over an active area of an FET, without reducing the length of original first patterned photoresist.

摘要翻译： 多晶硅或其他材料使用两层光致抗蚀剂和光刻胶蚀刻工艺（如灰化）进行定向修整。 在晶片上图案化第一层光致抗蚀剂。 第一图案化光致抗蚀剂的部分被第二层光致抗蚀剂覆盖。 修整光致抗蚀剂以减小第一图案化光致抗蚀剂的暴露部分的尺寸，而不减小第一图案化光致抗蚀剂的被覆盖部分的尺寸。 去除第二层光致抗蚀剂。 选择性蚀刻的图案化的第一层光致抗蚀剂用作处理掩模以限定下面的材料中的结构。 在特定实施例中，第二光致抗蚀剂覆盖栅极光致抗蚀剂的端盖部分。 定向微调在FET的有源区域上减小多晶硅栅结构的宽度（即栅极长度），而不会减小原始的第一图案化光致抗蚀剂的长度。

公开(公告)号：US6127225A

公开(公告)日：2000-10-03

申请号：US459746

申请日：1999-12-10

申请人： David Kuan-Yu Liu ,  Ting-wah Wong

发明人： David Kuan-Yu Liu ,  Ting-wah Wong

IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0425 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11517 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7885

摘要： A nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A select transistor can have a source which also acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor operates as a charge injector. The charge injector provides electrons for substrate hot electron injection of electrons onto the floating gate for programming. The cell depletion/inversion region may be extended by forming a capacitor as an extension of the control gate over the substrate between the source and channel of said sense transistor.

摘要翻译： 高度可伸缩的非易失性存储单元包括形成在三阱中的单元。 选择晶体管可以具有也用作横向双极晶体管的发射极的源极。 横向双极晶体管用作电荷注入器。 电荷注入器提供电子用于衬底热电子注入到浮动栅极上用于编程。 可以通过在所述感测晶体管的源极和沟道之间的衬底上形成作为控制栅极的延伸的电容器来扩展电解槽耗尽/反转区域。

公开(公告)号：US07557889B2

公开(公告)日：2009-07-07

申请号：US11855214

申请日：2007-09-14

申请人： Jin-Lan Lin ,  Kuan-Yu Liu

发明人： Jin-Lan Lin ,  Kuan-Yu Liu

IPC分类号： G02F1/1345

CPC分类号： G02F1/13452 ,  G02F1/1345

摘要： A liquid crystal panel structure includes a liquid crystal panel, a plurality of first and second contact terminals, and a plurality of first and second peripheral wirings. The liquid crystal display has a display area and a non-display area. The non-display area has at least one driving chip lamination area. The first and second contact terminals are allocated in the lamination area of the driving chip. The first peripheral wirings are allocated on the non-display area, and the first contact terminals are electrically connected to the pixels of the display area. The liquid crystal panel can selectively provides allocation of two types of driving chips, such that the liquid crystal panel can be applied to single or dual display module.

摘要翻译： 液晶面板结构包括液晶面板，多个第一和第二接触端子以及多个第一和第二外围布线。 液晶显示器具有显示区域和非显示区域。 非显示区域具有至少一个驱动芯片层叠区域。 第一和第二接触端子被分配在驱动芯片的层叠区域中。 第一外围布线被分配在非显示区域上，并且第一接触端子电连接到显示区域的像素。 液晶面板可以选择性地提供两种驱动芯片的分配，使得液晶面板可以应用于单显示模块或双显示模块。