公开(公告)号：US20100019037A1

公开(公告)日：2010-01-28

申请号：US12365899

申请日：2009-02-05

申请人： Chih-Wei Lai ,  Kuen-Bin Lai ,  Chi-Tai Wu

发明人： Chih-Wei Lai ,  Kuen-Bin Lai ,  Chi-Tai Wu

IPC分类号： G06K7/01

CPC分类号： G06F13/385 ,  Y02D10/14 ,  Y02D10/151

摘要： A method for dynamically managing a removable device includes the following steps: generating a device insertion interrupt to indicate that the removable device has been coupled to a connection interface when detecting an insert event corresponding to the removable device; clearing the device insertion interrupt before a processing mechanism corresponding to the connection interface handles the device insertion interrupt; and identifying a specification of the removable device to dynamically manage the removable device according to the specification; wherein when the specification corresponds to a first specification, a first management scheme is activated to manage the removable device, when the specification corresponds to a second specification, a second management scheme is activated to manage the removable device, and the first specification is different from the second specification.

摘要翻译： 一种用于动态管理可移动设备的方法包括以下步骤：当检测到与可移动设备相对应的插入事件时，产生设备插入中断以指示可移动设备已经耦合到连接接口; 在与连接接口对应的处理机制处理设备插入中断之前清除设备插入中断; 以及根据说明书识别可拆卸设备的动态管理可移动设备的规范; 其中当所述规范对应于第一规范时，启动第一管理方案以管理所述可移动设备，当所述规范对应于第二规范时，第二管理方案被激活以管理所述可移除设备，并且所述第一规范不同于 第二个规格。

公开(公告)号：US07605629B2

公开(公告)日：2009-10-20

申请号：US11749757

申请日：2007-05-17

申请人： Tung-Chen Kuo ,  Kuen-Bin Lai

发明人： Tung-Chen Kuo ,  Kuen-Bin Lai

IPC分类号： H03H11/26

CPC分类号： H03H11/26

摘要： Disclosed is an adjusting circuit for determining a target delay clock signal of a delay circuit having a plurality of delay units. The delay circuit generates a plurality of delay clock signals, and the adjusting circuit includes: a difference signal generating circuit, for generating a plurality of difference signals according to a reference clock signal and the delay clock signals; a delay processing circuit, coupled to the difference signal generating circuit, for determining the target delay clock signal by computing a corresponding number of delay units for a specific phase of the reference clock signal according to the difference signals; wherein the target delay clock signal is one of the delay clock signals.

摘要翻译： 公开了一种用于确定具有多个延迟单元的延迟电路的目标延迟时钟信号的调整电路。 延迟电路产生多个延迟时钟信号，调整电路包括：差信号发生电路，用于根据参考时钟信号和延迟时钟信号产生多个差分信号; 延迟处理电路，其耦合到所述差分信号发生电路，用于根据所述差分信号计算所述参考时钟信号的特定相位的相应数量的延迟单元来确定所述目标延迟时钟信号; 其中目标延迟时钟信号是延迟时钟信号之一。

公开(公告)号：US20070283064A1

公开(公告)日：2007-12-06

申请号：US11723136

申请日：2007-03-16

申请人： Kuen-Bin Lai

发明人： Kuen-Bin Lai

IPC分类号： G06F13/362

CPC分类号： G06F13/364 ,  G06F13/1605

摘要： The invention discloses an arbiter for arbitrating the mastership of a bus. The bus is coupled to a plurality of masters. The arbiter includes a request detection unit, a latency count unit, a grant generation unit, and an arbitration control unit. The request detection unit is used for detecting a plurality of request signals corresponding to the masters. According to a latency cycle of each request signal, the latency count unit counts the decayed latency of each request signal and further compares the decayed latency of each request signal, so as to determine the level of priority given to a designated master. Accordingly, the arbitration control unit is configured to control the grant generation unit to selectively generate a grant signal, such that the designated master with a higher level of priority will obtain the mastership of the bus based on the grant signal.

摘要翻译： 本发明公开了一种仲裁器，用于仲裁总线的掌握。 总线耦合到多个主机。 仲裁器包括请求检测单元，延迟计数单元，授权生成单元和仲裁控制单元。 请求检测单元用于检测对应于主设备的多个请求信号。 根据每个请求信号的延迟周期，等待时间计数单元对每个请求信号的衰减延迟进行计数，并进一步比较每个请求信号的衰减延迟，以便确定给予指定主机的优先级。 因此，仲裁控制单元被配置为控制授权生成单元选择性地生成授权信号，使得具有较高优先级的指定主机将基于授权信号获得总线的掌握。

公开(公告)号：US07975157B2

公开(公告)日：2011-07-05

申请号：US12248029

申请日：2008-10-08

申请人： Lian-Chun Lee ,  Jian-Fan Wei ,  Kuen-Bin Lai ,  Chi-Tai Wu ,  Chien-Hui Chen

发明人： Lian-Chun Lee ,  Jian-Fan Wei ,  Kuen-Bin Lai ,  Chi-Tai Wu ,  Chien-Hui Chen

IPC分类号： G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/325

摘要： A card reader with power-saving function is used for being inserted with a memory card so that a computer can access the memory card through the card reader. When the memory card is inserted in the card reader, the card reader is enabled to operate. On the other hand, when the memory card is not inserted in the card reader, the card reader enters to a power-down mode for saving power.

摘要翻译： 使用具有省电功能的读卡器插入存储卡，以便计算机可以通过读卡器访问存储卡。 当存储卡插入读卡器时，读卡器被启用。 另一方面，当存储卡未插入读卡器时，读卡器进入省电模式以节省电力。

公开(公告)号：US20100023789A1

公开(公告)日：2010-01-28

申请号：US12248029

申请日：2008-10-08

申请人： Lian-Chun Lee ,  Jian-Fan Wei ,  Kuen-Bin Lai ,  Chi-Tai Wu ,  Chien-Hui Chen

发明人： Lian-Chun Lee ,  Jian-Fan Wei ,  Kuen-Bin Lai ,  Chi-Tai Wu ,  Chien-Hui Chen

IPC分类号： G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/325

摘要： A card reader with power-saving function is used for being inserted with a memory card so that a computer can access the memory card through the card reader. When the memory card is inserted in the card reader, the card reader is enabled to operate. On the other hand, when the memory card is not inserted in the card reader, the card reader enters to a power-down mode for saving power.

摘要翻译： 具有省电功能的读卡器用于插入存储卡，以便计算机可以通过读卡器访问存储卡。 当存储卡插入读卡器时，读卡器被启用。 另一方面，当存储卡未插入读卡器时，读卡器进入省电模式以节省电力。

公开(公告)号：US20070273422A1

公开(公告)日：2007-11-29

申请号：US11749757

申请日：2007-05-17

申请人： Tung-Chen Kuo ,  Kuen-Bin Lai

发明人： Tung-Chen Kuo ,  Kuen-Bin Lai

IPC分类号： H03H11/26

CPC分类号： H03H11/26

摘要： Disclosed is an adjusting circuit for determining a target delay clock signal of a delay circuit having a plurality of delay units. The delay circuit generates a plurality of delay clock signals, and the adjusting circuit includes: a difference signal generating circuit, for generating a plurality of difference signals according to a reference clock signal and the delay clock signals; a delay processing circuit, coupled to the difference signal generating circuit, for determining the target delay clock signal by computing a corresponding number of delay units for a specific phase of the reference clock signal according to the difference signals; wherein the target delay clock signal is one of the delay clock signals.

摘要翻译： 公开了一种用于确定具有多个延迟单元的延迟电路的目标延迟时钟信号的调整电路。 延迟电路产生多个延迟时钟信号，调整电路包括：差信号发生电路，用于根据参考时钟信号和延迟时钟信号产生多个差分信号; 延迟处理电路，其耦合到所述差分信号发生电路，用于根据所述差分信号计算所述参考时钟信号的特定相位的相应数量的延迟单元来确定所述目标延迟时钟信号; 其中目标延迟时钟信号是延迟时钟信号之一。