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公开(公告)号：US06191661B1
公开(公告)日：2001-02-20
申请号：US09218223
申请日：1998-12-21
IPC分类号： H03B536
摘要： There is disclosed an oscillator circuit in which the first capacitor is connected between the input side of a CMOS inverter in a quartz oscillator circuit and a higher potential side, the second load capacitor is connected between the input side of the inverter and a lower potential side, the third load capacitor is connected between the output side of the inverter and the higher potential side, and the fourth load capacitor is connected between the output side of the inverter and the lower potential side, so that variation in amplitudes of the voltage sources synchronized with the oscillation can be reduced with the realization of lower current consumption. There is also disclosed an oscillator circuit of reduced circuit scale. A CMOS inverter for producing oscillations an AC coupling capacitor, and a buffer circuit are formed on one chip. A protective circuit that has been heretofore required at the input terminal portion of the buffer circuit can be dispensed with. Therefore, the capacity of the AC coupling capacitor can be reduced. Consequently, the circuit scale can be decreased.
摘要翻译： 公开了一种振荡器电路，其中第一电容器连接在石英振荡器电路中的CMOS反相器的输入侧和较高电位侧之间，第二负载电容器连接在逆变器的输入侧和较低电位侧 ，第三负载电容器连接在逆变器的输出侧和较高电位侧之间，第四负载电容器连接在逆变器的输出侧和下电位侧之间，使得电压源的振幅的变化同步 随着振荡可以减少，实现更低的电流消耗。 还公开了一种减小电路规模的振荡电路。 在一个芯片上形成用于产生AC耦合电容器的振荡的CMOS反相器和缓冲电路。 可以省略在缓冲电路的输入端部分所需的保护电路。 因此，可以减小交流耦合电容器的容量。 因此，可以减小电路规模。
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公开(公告)号：US06731169B2
公开(公告)日：2004-05-04
申请号：US10326369
申请日：2002-12-20
IPC分类号： H03F345
CPC分类号： H03F3/3028 , H03F3/45179 , H03F3/45183 , H03F3/4521 , H03F2203/45394
摘要： The first amplifier circuit D1 is formed by connecting drains of a pair of N-channel MOS transistors forming the first current mirror circuit CM1 respectively to the drains of P-channel MOS transistors 1 and 2 as a differential input portion, and the second amplifier circuit D2 is formed by connecting drains of a pair of P-channel MOS transistors forming the second current mirror circuit CM2 respectively to the drains of N-channel MOS transistors 5 and 6 as a differential amplifier circuit. The first and second differential amplifier circuits D1 and D2 can amplify the first and second signals having cycles corresponding with each other with their duty ratios kept unchanged regardless of their operating point potentials. Further, the two outputs are combined into one output to suppress variation of the operating point potential of the output attributable to process-related factors, fluctuation of the power supply potential due to the oscillating operation and the like.
摘要翻译： 第一放大电路D1通过将构成第一电流镜电路CM1的一对N沟道MOS晶体管的漏极分别连接到作为差分输入部的P沟道MOS晶体管1,2的漏极而形成，并且第二放大电路 通过将形成第二电流镜电路CM2的一对P沟道MOS晶体管的漏极分别连接到N沟道MOS晶体管5和6的漏极作为差分放大器电路来形成D2。 第一和第二差分放大器电路D1和D2可以放大具有彼此对应的周期的第一和第二信号，其占空比保持不变，而与它们的工作点电位无关。 此外，两个输出组合成一个输出，以抑制归因于处理相关因素的输出的工作点电位的变化，由于振荡操作引起的电源电位的波动等。
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公开(公告)号：US06329884B1
公开(公告)日：2001-12-11
申请号：US09168906
申请日：1998-10-08
IPC分类号： H03B536
摘要： There is disclosed an oscillator circuit in which the first capacitor is connected between the input side of a CMOS inverter in a quartz oscillator circuit and a higher potential side, the second load capacitor is connected between the input side of the inverter and a lower potential side, the third load capacitor is connected between the output side of the inverter and the higher potential side, and the fourth load capacitor is connected between the output side of the inveter and the lower potential side, so that variation in amplitudes of the voltage sources synchronized with the oscillation can be reduced with the realization of lower current consumption.
摘要翻译： 公开了一种振荡器电路，其中第一电容器连接在石英振荡器电路中的CMOS反相器的输入侧和较高电位侧之间，第二负载电容器连接在逆变器的输入侧和较低电位侧 ，第三负载电容器连接在逆变器的输出侧和较高电位侧之间，第四负载电容器连接在输入端的输出侧和下电位侧之间，使得电压源的振幅的变化同步 随着振荡可以减少，实现更低的电流消耗。
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公开(公告)号：US6072333A
公开(公告)日：2000-06-06
申请号：US185773
申请日：1998-11-04
IPC分类号： H03K19/0175 , H03K19/00 , H03K19/003 , H03K19/094
CPC分类号： H03K19/0013 , H03K19/00323 , H03K19/09429
摘要： The drains of P- and N-channel MOS transistors 1 and 2 are connected to each other. An output terminal is formed at the node of the drains. Each of first and second amplifier stages 4 and 5 is configured by cascading an n number of CMOS inverters. The amplifier stages drive first and second last-stage CMOS inverters 6 and 7 to drive the P- and N-channel MOS transistors 1 and 2, respectively. A dummy CMOS inverter 8 is disposed so that the input is connected to the node of the second amplifier stage 5 and the second last-stage CMOS inverter 7. The load of the second amplifier stage 5 is equal to that of the first amplifier stage 4. The drivabilities of the CMOS inverters of the same stage in the first and second amplifier stages 4 and 5 are made equal to each other. According to this configuration, the number of CMOS inverters which must be checked in a process of adjusting the duty can be reduced.
摘要翻译： P沟道和N沟道MOS晶体管1和2的漏极相互连接。 输出端子形成在排水管的节点处。 第一和第二放大器级4和5中的每一个通过级联n个CMOS反相器来配置。 放大器级驱动第一和第二后级CMOS反相器6和7，分别驱动P沟道MOS晶体管和N沟道MOS晶体管1和2。 虚设CMOS反相器8被布置成使得输入端连接到第二放大器级5和第二级后级CMOS反相器7的节点。第二放大级5的负载等于第一放大级4的负载 使第一和第二放大器级4和5中相同级的CMOS反相器的驱动能力彼此相等。 根据该结构，可以减少在调整占空比的过程中必须检查的CMOS反相器的数量。
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公开(公告)号：US06411172B1
公开(公告)日：2002-06-25
申请号：US09753822
申请日：2001-01-03
IPC分类号： H03B536
摘要： There is disclosed an oscillator circuit in which the first capacitor is connected between the input side of a CMOS inverter in a quartz oscillator circuit and a higher potential side, the second load capacitor is connected between the input side of the inverter and a lower potential side, the third load capacitor is connected between the output side of the inverter and the higher potential side, and the fourth load capacitor is connected between the output side of the inverter and the lower potential side, so that variation in amplitudes of the voltage sources synchronized with the oscillation can be reduced with the realization of lower current consumption. There is also disclosed an oscillator circuit of reduced circuit scale. A CMOS inverter for producing oscillations, an AC coupling capacitor, and a buffer circuit are formed on one chip. A protective circuit that has been heretofore required at the input terminal portion of the buffer circuit can be dispensed with. Therefore, the capacity of the AC coupling capacitor can be reduced. Consequently, the circuit scale can be decreased.
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公开(公告)号：US06556094B2
公开(公告)日：2003-04-29
申请号：US10015823
申请日：2001-10-26
IPC分类号： H03B532
CPC分类号： H03K3/0307 , H03B5/36
摘要： An oscillator circuit adapted for a piezoelectric oscillator which has a weak oscillation output for generating high frequencies is provided. The speed of operation of the oscillator circuit is increased. An integrated circuit for such an oscillator circuit is also provided. The oscillator circuit has an amplifier portion consisting of CMOS inverters connected in cascade. MOS transistors forming the CMOS inverters have channel widths that decrease successively from the first stage to the last stage to improve the amplification factor of the amplifier portion at high frequencies. This makes it possible to amplify weak oscillation output from the quartz oscillator (XL). A filter circuit produces a peak of negative resistance at a frequency higher than conventional. This permit oscillation operation at higher frequencies.
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公开(公告)号：US06242980B1
公开(公告)日：2001-06-05
申请号：US09195473
申请日：1998-11-18
IPC分类号： H03F345
CPC分类号： H03F3/3028 , H03F3/45179 , H03F3/45183 , H03F3/4521 , H03F2203/45394
摘要： The first amplifier circuit D1 is formed by connecting drains of a pair of N-channel MOS transistors forming the first current mirror circuit CM1 respectively to the drains of P-channel MOS transistors 1 and 2 as a differential input portion, and the second amplifier circuit D2 is formed by connecting drains of a pair of P-channel MOS transistors forming the second current mirror circuit CM2 respectively to the drains of N-channel MOS transistors 5 and 6 as a differential amplifier circuit. The first and second differential amplifier circuits D1 and D2 can amplify the first and second signals having cycles corresponding with each other with their duty ratios kept unchanged regardless of their operating point potentials. Further, the two outputs are combined into one output to suppress variation of the operating point potential of the output attributable to process-related factors, fluctuation of the power supply potential due to the oscillating operation and the like.
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公开(公告)号：US6025757A
公开(公告)日：2000-02-15
申请号：US191836
申请日：1998-11-13
摘要： There is disclosed an oscillator circuit comprising the first load capacitor with one electrode there of being connected with an input side of a CMOS inverter within a quartz oscillator circuit, and the second load capacitor with one electrode there of being connected with the output side of the inverter, wherein the inverter is coupled to a lower potential side via a current-limiting device, and the other electrodes of the first and second load capacitors are coupled to a lower potential side via the above-described current-limiting device. Thus, variations in the power-supply voltages synchronized with oscillation are reduced with realization of lower current consumption.
摘要翻译： 公开了一种振荡器电路，其包括第一负载电容器，其中一个电极与石英振荡器电路内的CMOS反相器的输入侧连接，并且第二负载电容器的一个电极与其中的一个电极连接， 逆变器，其中逆变器经由限流装置耦合到较低电位侧，并且第一和第二负载电容器的其它电极经由上述限流装置耦合到较低电位侧。 因此，通过实现更低的电流消耗来降低与振荡同步的电源电压的变化。
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