公开(公告)号：US20130120035A1

公开(公告)日：2013-05-16

申请号：US13297658

申请日：2011-11-16

申请人： Feng Wei KUO ,  Kyle YEN ,  Huan-Neng CHEN ,  Yen-Jen CHEN ,  Chewn-Pu JOU

发明人： Feng Wei KUO ,  Kyle YEN ,  Huan-Neng CHEN ,  Yen-Jen CHEN ,  Chewn-Pu JOU

IPC分类号： H03L7/08

CPC分类号： H03L7/095

摘要： A lock detector for a PLL circuit includes a first signal counting circuit, a second signal counting circuit, a comparator, and a lock status unit. The first signal counting circuit is configured to define a plurality of observation periods according to a first oscillating signal and a predetermined cycle value. The second signal counting circuit is configured to determine a maximum counter value according to a second oscillating signal within each of the observation periods, and the second oscillating signal is generated in relation to the first oscillating signal. The comparator is configured to determine, for each of the observation periods, whether the maximum counter value equals the predetermined cycle value. The lock status unit is configured to generate a lock signal based on the maximum counter value being equal to the predetermined cycle value for a predetermined number of consecutive ones of the observation periods.

摘要翻译： 用于PLL电路的锁定检测器包括第一信号计数电路，第二信号计数电路，比较器和锁定状态单元。 第一信号计数电路被配置为根据第一振荡信号和预定周期值来定义多个观察周期。 第二信号计数电路被配置为根据每个观测周期内的第二振荡信号来确定最大计数器值，并且相对于第一振荡信号产生第二振荡信号。 比较器被配置为为每个观察周期确定最大计数器值是否等于预定周期值。 锁定状态单元被配置为基于最大计数器值等于预定数量的连续观察周期中的预定周期值的锁定信号。

公开(公告)号：US08456207B1

公开(公告)日：2013-06-04

申请号：US13297658

申请日：2011-11-16

申请人： Feng Wei Kuo ,  Kyle Yen ,  Huan-Neng Chen ,  Yen-Jen Chen ,  Chewn-Pu Jou

发明人： Feng Wei Kuo ,  Kyle Yen ,  Huan-Neng Chen ,  Yen-Jen Chen ,  Chewn-Pu Jou

IPC分类号： H03L7/06

CPC分类号： H03L7/095

摘要： A lock detector for a PLL circuit includes a first signal counting circuit, a second signal counting circuit, a comparator, and a lock status unit. The first signal counting circuit is configured to define a plurality of observation periods according to a first oscillating signal and a predetermined cycle value. The second signal counting circuit is configured to determine a maximum counter value according to a second oscillating signal within each of the observation periods, and the second oscillating signal is generated in relation to the first oscillating signal. The comparator is configured to determine, for each of the observation periods, whether the maximum counter value equals the predetermined cycle value. The lock status unit is configured to generate a lock signal based on the maximum counter value being equal to the predetermined cycle value for a predetermined number of consecutive ones of the observation periods.

摘要翻译： 用于PLL电路的锁定检测器包括第一信号计数电路，第二信号计数电路，比较器和锁定状态单元。 第一信号计数电路被配置为根据第一振荡信号和预定周期值来定义多个观察周期。 第二信号计数电路被配置为根据每个观测周期内的第二振荡信号来确定最大计数器值，并且相对于第一振荡信号产生第二振荡信号。 比较器被配置为为每个观察周期确定最大计数器值是否等于预定周期值。 锁定状态单元被配置为基于最大计数器值等于预定数量的连续观察周期中的预定周期值的锁定信号。