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    DIVIDER-LESS PHASE LOCKED LOOP (PLL)
    1.
    发明申请
    DIVIDER-LESS PHASE LOCKED LOOP (PLL) 有权
    无相位锁相环（PLL）

    公开(公告)号：US20140049329A1

    公开(公告)日：2014-02-20

    申请号：US13586033

    申请日：2012-08-15

    申请人： Yen-Jen Chen ,  I-Ting Lee ,  Hsieh-Hung Hsieh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Shen-Luan Liu

    发明人： Yen-Jen Chen ,  I-Ting Lee ,  Hsieh-Hung Hsieh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Shen-Luan Liu

    IPC分类号： H03L7/099

    CPC分类号： H03K3/0322 ,  H03K3/0315 ,  H03L7/083 ,  H03L7/087 ,  H03L7/089 ,  H03L7/099

    摘要： One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulsePD) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulsePD signal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulsePD signal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.

    摘要翻译： 本文提供了一种用于无分频锁相环（PLL）和相关相位检测器（PD）的技术和系统。 在一些实施例中，接收脉冲相位检测器（pulsePD）信号，压控振荡器正差分（VCOP）信号和压控振荡器负差分（VCON）信号。 基于pulsePD信号，VCOP信号和VCON信号产生用于第一电荷泵（CP）的上升信号和下降信号以及用于第二CP的上升信号和下降信号。 例如，生成CP信号以分别控制第一CP和第二CP。 在一些实施例中，产生CP信号，使得CP有助于调整相对于pulsePD信号的VCON和VCOP信号的零交叉相位。 以这种方式，提供无分频PLL，从而减轻PLL功耗。

    Phase frequency detector circuit
    3.
    发明授权
    Phase frequency detector circuit 有权
    相位检波电路

    公开(公告)号：US08643402B2

    公开(公告)日：2014-02-04

    申请号：US13308274

    申请日：2011-11-30

    申请人： Yen-Jen Chen ,  I-Ting Lee ,  Feng Wei Kuo ,  Huan-Neng Chen ,  Chewn-Pu Jou

    发明人： Yen-Jen Chen ,  I-Ting Lee ,  Feng Wei Kuo ,  Huan-Neng Chen ,  Chewn-Pu Jou

    IPC分类号： H03D13/00 ,  H03D3/00

    CPC分类号： H03D13/00 ,  H03D13/004 ,  H03L7/087 ,  H03L7/089 ,  H03L7/10

    摘要： A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal.

    摘要翻译： 相位频率检测器电路包括边缘检测器电路，多个相位频率检测器子电路和判定电路。 边缘检测器电路被配置为接收第一输入信号和第二输入信号。 判定电路被配置为基于边缘检测器电路的输出和多个相位频率检测器子电路的输出来检测盲状态是否退出。 响应于判定电路的结果，多个相位频率检测器子电路的对应的频率检测器子电路被配置为提供用于确定第一输入信号和第二输入信号之间的相位差的信号。

    Lock detector and method of detecting lock status for phase lock loop
    4.
    发明授权
    Lock detector and method of detecting lock status for phase lock loop 有权
    锁定检测器和检测锁相环锁定状态的方法

    公开(公告)号：US08456207B1

    公开(公告)日：2013-06-04

    申请号：US13297658

    申请日：2011-11-16

    申请人： Feng Wei Kuo ,  Kyle Yen ,  Huan-Neng Chen ,  Yen-Jen Chen ,  Chewn-Pu Jou

    发明人： Feng Wei Kuo ,  Kyle Yen ,  Huan-Neng Chen ,  Yen-Jen Chen ,  Chewn-Pu Jou

    IPC分类号： H03L7/06

    CPC分类号： H03L7/095

    摘要： A lock detector for a PLL circuit includes a first signal counting circuit, a second signal counting circuit, a comparator, and a lock status unit. The first signal counting circuit is configured to define a plurality of observation periods according to a first oscillating signal and a predetermined cycle value. The second signal counting circuit is configured to determine a maximum counter value according to a second oscillating signal within each of the observation periods, and the second oscillating signal is generated in relation to the first oscillating signal. The comparator is configured to determine, for each of the observation periods, whether the maximum counter value equals the predetermined cycle value. The lock status unit is configured to generate a lock signal based on the maximum counter value being equal to the predetermined cycle value for a predetermined number of consecutive ones of the observation periods.

    摘要翻译： 用于PLL电路的锁定检测器包括第一信号计数电路，第二信号计数电路，比较器和锁定状态单元。 第一信号计数电路被配置为根据第一振荡信号和预定周期值来定义多个观察周期。 第二信号计数电路被配置为根据每个观测周期内的第二振荡信号来确定最大计数器值，并且相对于第一振荡信号产生第二振荡信号。 比较器被配置为为每个观察周期确定最大计数器值是否等于预定周期值。 锁定状态单元被配置为基于最大计数器值等于预定数量的连续观察周期中的预定周期值的锁定信号。

    Battery power level inspection device co-constructed with system indicators of notebook computer and inspection method thereof
    6.
    发明授权
    Battery power level inspection device co-constructed with system indicators of notebook computer and inspection method thereof 有权
    电池功率电平检测装置与笔记本电脑的系统指示器及其检查方法共同构成

    公开(公告)号：US07554456B2

    公开(公告)日：2009-06-30

    申请号：US11370061

    申请日：2006-03-08

    申请人： Yen-Jen Chen

    发明人： Yen-Jen Chen

    IPC分类号： G08B21/00

    CPC分类号： G06F1/1616 ,  G06F1/1684 ,  G06F1/28

    摘要： A radio frequency IC tag is provided which is excellent in weatherability, dustproofness, waterproofness, and static protection and capable of making a communication distance long even though each antenna section is made small in configuration. A first antenna equipped with an IC chip is formed on an upper surface of a first spacer. A second antenna is formed on a lower surface of a top cover. A second spacer is shaped in hollow form. The first spacer and the top cover are disposed on both sides of the second spacer with the first antenna and the second antenna being opposite to each other. Each of the first spacer, the second spacer and the top cover is formed of a synthetic resin. Thus, the IC chip and each antenna section are not exposed to the outside and hence weatherability is enhanced.

    摘要翻译： 提供了一种射频IC标签，其耐候性，防尘性，防水性和静电保护性优异，并且即使每个天线部分的结构较小，也能够使通信距离变长。 配备有IC芯片的第一天线形成在第一间隔物的上表面上。 第二天线形成在顶盖的下表面上。 第二间隔件成形为中空形状。 第一间隔件和顶盖设置在第二间隔件的两侧，第一天线和第二天线彼此相对。 第一间隔件，第二间隔件和顶盖中的每个由合成树脂形成。 因此，IC芯片和每个天线部分不暴露于外部，因此耐候性提高。

    Combined exercise management and entertainment unit
    8.
    发明授权
    Combined exercise management and entertainment unit 有权
    组合运动管理和娱乐单位

    公开(公告)号：US07491153B2

    公开(公告)日：2009-02-17

    申请号：US11598637

    申请日：2006-11-14

    申请人： Chun-Hsing Li ,  Yen-Jen Chen

    发明人： Chun-Hsing Li ,  Yen-Jen Chen

    IPC分类号： A63B21/00

    CPC分类号： A63B24/0084 ,  A63B71/0622 ,  A63B2071/0625 ,  A63B2071/0627 ,  A63B2225/20 ,  A63B2225/50 ,  A63B2230/065 ,  A63B2230/202 ,  A63B2230/30 ,  A63B2230/70 ,  A63B2230/75 ,  G06F19/00 ,  G06Q50/22

    摘要： A combined exercise management and entertainment unit includes a sensor for sensing a user's body state during exercise and producing an exercise signal to a microprocessor, so as to calculate the user's calorie consumption during exercise each time and the accumulated calorie consumption; a personal characteristics database for storing data of a user's body physical characteristics; an exercise course memory for storing exercise courses set by the user, including the time period, item, and duration of an exercise to be done; a setting unit for the user to set the data of body physical characteristics to be stored in the personal characteristics database; and a play unit having an entertainment information memory for storing a plurality of entertainment information entries, which correspond to the exercise items set by the user and may be selectively played corresponding to the exercise item being done.

    摘要翻译： 组合的运动管理和娱乐单元包括用于在运动期间感测使用者的身体状态并向微处理器产生运动信号的传感器，以便计算每次运动期间用户的卡路里消耗量和累积卡路里消耗量; 用于存储用户身体物理特征的数据的个人特征数据库; 用于存储用户设置的运动课程的运动课程记忆，包括待完成的锻炼的时间段，项目和持续时间; 设置单元，用于设置要存储在个人特征数据库中的身体物理特性的数据; 以及播放单元，具有娱乐信息存储器，用于存储与用户设置的运动项目相对应的多个娱乐信息条目，并且可以根据正在完成的运动项目选择性地播放。

    Auto frequency calibration for a phase locked loop and method of use
    9.
    发明授权
    Auto frequency calibration for a phase locked loop and method of use 有权
    锁相环的自动频率校准和使用方法

    公开(公告)号：US08953730B2

    公开(公告)日：2015-02-10

    申请号：US13452138

    申请日：2012-04-20

    申请人： Yen-Jen Chen ,  Feng Wei Kuo ,  Huan-Neng Chen ,  Chewn-Pu Jou

    发明人： Yen-Jen Chen ,  Feng Wei Kuo ,  Huan-Neng Chen ,  Chewn-Pu Jou

    IPC分类号： H03D3/24

    CPC分类号： H03L7/0802 ,  G04F10/005 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0992 ,  H03L7/101 ,  H03L7/103 ,  H03L7/104 ,  H03L7/1976 ,  H03L2207/50 ,  H03M1/002 ,  H03M3/32

    摘要： A phase locked loop includes a phase difference detector configured to receive a reference frequency and a divider frequency and output a phase difference signal. The phase locked loop includes a code generator configured to receive the reference frequency and the phase difference signal, and output a coarse tuning signal and a reset signal. The phase locked loop includes a digital loop filter configured to receive the phase difference signal and output a fine tuning signal. The phase locked loop includes a voltage control oscillator configured to receive the coarse and fine tuning signals, and output an output frequency. The phase locked loop includes a divider configured to receive the reset signal, a divider number control signal and the output frequency, and output the divider frequency. The phase locked loop includes a delta-sigma modulator configured to receive a divisor ratio and the reset signal, and output divider number control signal.

    摘要翻译： 锁相环包括被配置为接收参考频率和分频器频率并输出相位差信号的相位差检测器。 锁相环包括被配置为接收参考频率和相位差信号的码发生器，并输出粗调谐信号和复位信号。 锁相环包括配置为接收相位差信号并输出​​微调信号的数字环路滤波器。 锁相环包括配置成接收粗调和微调信号并输出​​输出频率的压控振荡器。 锁相环包括分配器，用于接收复位信号，分频器数控制信号和输出频率，并输出分频器。 锁相环包括被配置为接收除数比和复位信号的delta-sigma调制器，并输出分频数控制信号。

    AUTO FREQUENCY CALIBRATION FOR A PHASE LOCKED LOOP AND METHOD OF USE
    10.
    发明申请
    AUTO FREQUENCY CALIBRATION FOR A PHASE LOCKED LOOP AND METHOD OF USE 有权
    用于相位锁定环的自动频率校准及其使用方法

    公开(公告)号：US20130278303A1

    公开(公告)日：2013-10-24

    申请号：US13452138

    申请日：2012-04-20

    申请人： Yen-Jen CHEN ,  Feng Wei KUO ,  Huan-Neng CHEN ,  Chewn-Pu JOU

    发明人： Yen-Jen CHEN ,  Feng Wei KUO ,  Huan-Neng CHEN ,  Chewn-Pu JOU

    IPC分类号： H03L7/08 ,  H03L7/00 ,  H03B19/00

    CPC分类号： H03L7/0802 ,  G04F10/005 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0992 ,  H03L7/101 ,  H03L7/103 ,  H03L7/104 ,  H03L7/1976 ,  H03L2207/50 ,  H03M1/002 ,  H03M3/32

    摘要： A phase locked loop includes a phase difference detector configured to receive a reference frequency and a divider frequency and output a phase difference signal. The phase locked loop includes a code generator configured to receive the reference frequency and the phase difference signal, and output a coarse tuning signal and a reset signal. The phase locked loop includes a digital loop filter configured to receive the phase difference signal and output a fine tuning signal. The phase locked loop includes a voltage control oscillator configured to receive the coarse and fine tuning signals, and output an output frequency. The phase locked loop includes a divider configured to receive the reset signal, a divider number control signal and the output frequency, and output the divider frequency. The phase locked loop includes a delta-sigma modulator configured to receive a divisor ratio and the reset signal, and output divider number control signal.

    摘要翻译： 锁相环包括被配置为接收参考频率和分频器频率并输出相位差信号的相位差检测器。 锁相环包括被配置为接收参考频率和相位差信号的码发生器，并输出粗调谐信号和复位信号。 锁相环包括配置为接收相位差信号并输出​​微调信号的数字环路滤波器。 锁相环包括配置成接收粗调和微调信号并输出​​输出频率的压控振荡器。 锁相环包括分配器，用于接收复位信号，分频器数控制信号和输出频率，并输出分频器。 锁相环包括被配置为接收除数比和复位信号的delta-sigma调制器，并输出分频数控制信号。